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Flow-based data packet filtering system and data packet filtering method by using Tilera multi-core accelerator card

A technology of filtering systems and data packets, applied in digital transmission systems, transmission systems, data exchange networks, etc., can solve problems such as low I/O performance, CPU performance problems, and increased main memory capacity, so as to improve efficiency and reduce pressure. , the effect of high portability

Active Publication Date: 2016-04-20
BEIHANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] (1) I / O performance problem: The I / O performance of the traditional data packet collection and processing method is low, which is not enough to meet the I / O requirements of high-speed links
[0004] (2) Main memory performance problem (main memory capacity: several 10Gb traffic is generated per second under the high-speed link. When data packets are collected, the demand for main memory space is large. If the processing of the traffic application layer is considered, the main memory The demand for capacity will increase exponentially; memory access bandwidth: the number of memory accesses for network traffic processing is proportional to the data packet data. Usually, a memory access requires hundreds of CPU clock cycles. In a high-speed network environment, the time interval between data packets is less than the memory access time, so it cannot meet the line-rate data packet processing requirements under a high-speed network)
[0005] (3) CPU performance problem: the processing capacity of the existing CPU cannot meet the data packet processing requirements of the line rate
[0007] Real-time traffic analysis in a 10G network environment requires processing massive amounts of data, which increases the difficulty of data processing

Method used

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  • Flow-based data packet filtering system and data packet filtering method by using Tilera multi-core accelerator card
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  • Flow-based data packet filtering system and data packet filtering method by using Tilera multi-core accelerator card

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Embodiment

[0131] An embodiment of the present invention is given below to illustrate the process of data packet filtering in the present invention. The specific packet filtering steps are as follows:

[0132] Step 1, the onboard mPIPE unit of the Tilera multi-core accelerator card on the general host obtains the data packet PA sent from the network device in , mPIPE gives all received packets pa in According to packet PA in The order of arrival is time stamped, and the data packets at this time are

[0133] PA={packet 1 ,packet 2 ,packet 3 ,packet 4 ,packet 5 ,packet6 ,...,packet M}.

[0134] Read all packets from mPIPE unit

[0135] PA={packet 1 ,packet 2 ,packet 3 ,packet 4 ,packet 5 ,packet 6 ,...,packet M}, and all packets

[0136] PA={packet 1 ,packet 2 ,packet 3 ,packet 4 ,packet 5 ,packet 6 ,...,packet M} stored in the buffer.

[0137] Step 2, for all the above packets

[0138] PA={packet 1 ,packet 2 ,packet 3 ,packet 4 ,packet 5 ,packet 6 ,...,pa...

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Abstract

The invention discloses a flow-based data packet filtering system and data packet filtering method by using a Tilera multi-core accelerator card. The data packet filtering system is composed of a data packet acquisition module, a five-element content extraction module, a rule matching module, a flow table lookup and updating module, a PCIe data transmission module, a PCIe data package receiving module and a data packet storage module. In addition, the data packet filtering method is characterized in that data packet acquisition is carried out based on a heterogeneous system formed by the Tilera multi-core processor and a universal host and data packet filtering is carried out based a flow. Data packet acquisition in the mPIPE of the Tilera multi-core accelerator card is carried out; flow-based data packet filtering is realized by using the flow table on Tilera; the filtered data packet is transmitted to a universal computer by PCIe driving; and the data packet storage is realized on the universal computer. The system and method are suitable for the on-line flow analysis and storage in a ten-gigabit network environment.

Description

technical field [0001] The invention relates to a flow-based data packet filtering method under the environment of 10 gigabit network bandwidth. To be more precise, the traffic collection, flow-based data packet filtering and data packet storage methods under the heterogeneous architecture composed of the general host and the Tilera multi-core accelerator card embedded in the PCIe interface of the general host are used. Background technique [0002] With the development of the Internet, 10G network technology has gradually become the mainstream bandwidth technology, which brings challenges to network traffic management, real-time traffic analysis and traffic storage. Traditional network traffic collection and processing is the combination of ordinary network card and data collection software, such as Libpcap (library packet capture, data packet capture function library), BPF (Berkeley Packet Filter, Berkeley packet filter) and so on. However, as the link bandwidth increases...

Claims

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Application Information

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IPC IPC(8): H04L12/813H04L47/20
CPCH04L47/20
Inventor 李巍于秀芬李云春
Owner BEIHANG UNIV
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