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Technique for stabilizing shape and form of grid in RFLDMOS technology

A process method and gate technology, applied in the field of gate manufacturing, can solve problems such as unstable gate morphology and RFLDMOS threshold voltage instability

Active Publication Date: 2016-04-27
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved in the present invention is to provide a process method for stabilizing gate morphology in the RFLDMOS process, so as to solve the problem that the threshold voltage of RFLDMOS is unstable due to unstable gate morphology in the RFLDMOS manufacturing process

Method used

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  • Technique for stabilizing shape and form of grid in RFLDMOS technology
  • Technique for stabilizing shape and form of grid in RFLDMOS technology
  • Technique for stabilizing shape and form of grid in RFLDMOS technology

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Embodiment 1

[0042] A process method for stabilizing gate morphology in an RFLDMOS process, comprising the steps of:

[0043] 1) On the P-type lightly doped epitaxial layer 2, grow a layer with a thickness of The gate oxide silicon forms the gate oxide layer 3, and the source end side of the gate oxide layer is etched to a thickness of A thin gate oxide layer is formed.

[0044] In other embodiments of the present invention, the thickness and shape of the gate oxide layer 3 can be adjusted according to the requirements of the device.

[0045] 2) Depositing a layer of polysilicon on the gate oxide layer to form a polysilicon gate 4 with a thickness of 0.3 μm.

[0046] In other embodiments of the present invention, the polysilicon gate 4 has a thickness of 0.25-0.35 μm, and its thickness can be adjusted according to the requirements of the device.

[0047] 3) The first photolithography is performed on the polysilicon gate 4 to define the source end of the device, the first etching is pe...

Embodiment 2

[0051] A process method for stabilizing gate morphology in the RFLDMOS process, wherein the drain end of the RFLDMOS has thick gate oxide and the source end has thin gate oxide, the steps of the process method are as follows:

[0052] 1) On the P-type lightly doped epitaxial layer 2, grow a layer with a thickness of The gate oxide layer 3 is formed by gate silicon oxide, and the gate oxide layer is etched so that the thickness of the gate oxide layer at the source end is During etching, a thick gate oxide region 31 remains at the source end, the gate oxide of the thick gate oxide region 31 is not etched, and its thickness is still

[0053] 2) A layer of polysilicon is deposited on the gate oxide layer 3 to form a polysilicon gate 4 with a thickness of 0.3 μm.

[0054] In other embodiments of the present invention, the thickness of the polysilicon gate 4 is 0.25-0.35 μm, which can be adjusted according to the requirements of the device.

[0055]3) Carry out the first phot...

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Abstract

The invention provides a technique for stabilizing the shape and form of a grid in an RFLDMOS technology. The technique comprises the following steps: (1) growing a gate silicon oxide layer on a P-type lightly doped epitaxial layer to form a gate oxide layer; (2) depositing a polysilicon layer on the gate oxide layer to form a polysilicon gate; (3) defining one end of a source terminal and a drain terminal of the device grid through primary photolithography, carrying out first etching, removing a photoresist and forming one half of the grid; and (4) defining the other end of the device grid through secondary photolithography, carrying out second etching and removing the photoresist. The grid is formed by a two-step etching method; and compared with a method for forming the grid through one-step etching in the prior art, the technique reduces the clear ratio (clear ratio) of single etching, and can relatively stably control the shape and form of the grid for etching, so that the target of stabilizing a threshold voltage is achieved.

Description

technical field [0001] The invention relates to the field of manufacturing of semiconductor integrated circuits, in particular to a method for manufacturing gates in RFLDMOS. Background technique [0002] RFLDMOS (Laterally Diffused Metal-Oxide Semiconductor), a high-power radio frequency device used for base stations, etc., includes the following structure: source 13, drain 14, gate 15, channel 16 and base, and Faraday shielding ring 17. For detailed structure, see figure 1 . The device is located in the epitaxial layer 12 grown on the heavily doped substrate 11, the drain end 14 has a longer drift region to obtain the required breakdown voltage, and the Faraday shielding ring 17 is formed by adding a thin layer of dielectric and Composed of sheet metal. The channel 16 is formed by implanting P-type ions from the edge of the source end of the self-aligned gate 15, and is formed by long-term high-temperature advancement, and its lead-out end is on the same side of the sour...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28H01L21/336H01L29/423
CPCH01L21/28H01L29/4232H01L29/66681
Inventor 蔡莹
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP