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Instruction scheduling method and device

An instruction scheduling and instruction technology, applied in the direction of machine execution devices, concurrent instruction execution, etc., can solve the problems of ME performance degradation, large degree of disorder, idle kernel pipeline, etc., to improve overall performance, reduce degree of disorder, and avoid instructions empty shot effect

Active Publication Date: 2016-07-20
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Traditional multi-threaded network processors all use high-speed cache (cache) to store microcode instructions. Since cache access has a certain probability of miss, the method of fetching instructions and scheduling instructions for coarse-grained multi-threaded ME is not efficient. When , the empty beat of the instruction will cause the core pipeline to be idle, which will lead to the decline of ME performance
[0005] In addition, although ME with a fine-grained multi-threaded structure can use thread switching to hide the problem of empty finger fetching, due to frequent thread switching, it will aggravate the out-of-order degree of ME processing messages to a certain extent.
The degree of disorder will become larger and larger, which will eventually increase the degree of disorder of packets entering and leaving the ME, which will put greater pressure on the subsequent order-keeping module of the network processor, resulting in a decline in the overall system performance.

Method used

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Examples

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Embodiment 1

[0068] image 3 It is a schematic diagram of the ME command scheduling process described in Embodiment 1 of the present invention, as image 3 As shown, the method includes the following steps:

[0069] Step 301, the fetching module parses the fetching pc information carried in the new package, and issues a fetching request;

[0070] Here, the instruction fetch module is composed of four queues plus an arbitration module, the queue caches the corresponding instruction fetch request, and sends an instruction fetch request to the cache after 4 to 1 arbitration. Considering the actual processing of packet instruction fetch requests, the four queues correspond to four instruction fetch pc requests respectively, new packet instruction fetch pkt_pc, message sequential instruction fetch, jump instruction fetch, and repeated instruction fetch after cache miss.

[0071] In actual packet processing, for a new packet, parse the packet information, extract the instruction fetch pc, and ...

Embodiment 2

[0084] In this embodiment, the instruction scheduling device completes the prefetching of instructions through the instruction fetch module and the control state machine module, Figure 4 It is a schematic diagram of the instruction prefetching flow chart of the ME described in Embodiment 2 of the present invention, as shown in Figure 4 As shown, the method includes the following steps:

[0085] Step 401, the new packet enters the ME, the instruction scheduling device parses and extracts the instruction fetch pc, and sends an instruction fetch request to the instruction fetch module;

[0086] Step 402, the instruction fetch module sends an instruction fetch request to the cache through arbitration scheduling;

[0087] In step 403, the instruction is returned and loaded into the instruction register module, and is scheduled to be sent to the pipeline. During execution, the control state machine module monitors the instruction issuance of each thread. When there is only one ...

Embodiment 3

[0097] In this embodiment, the instruction scheduling device manages the instruction scheduling of each thread through the instruction scheduling module. The instruction scheduling module completes thread-level instruction scheduling according to the LRU algorithm (LeastRecentlyUsed), and transmits instructions from the cache to the pipeline to ensure that the packets that enter the ME first are executed first.

[0098] Figure 6 It is a schematic flow diagram of ME thread-level instruction scheduling described in Embodiment 3 of the present invention, as shown in Figure 6 As shown, the method includes the following steps:

[0099] Step 601, extracting the thread number of the new package, and writing it into the base queue;

[0100] The essence of the thread-level instruction scheduling strategy of the present invention is to dynamically update the RR round-robin scheduling of the base. When the value of the base is set as the value of the corresponding thread, the thread ...

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Abstract

The embodiment of the invention discloses an instruction scheduling method and device. The method comprises the following steps: pre-fetching and caching a preset quantity of instructions of threads; and performing instruction scheduling according to thread states and the cached pre-fetched instructions. In the embodiment of the invention, instruction pre-fetching is executed firstly, and scheduling is performed according the pre-fetched instructions, so that instruction dummy operation can be avoided; the instruction scheduling efficiency is increased; and the overall performance of an ME (Micro Engine) is improved. Moreover, if instruction priority scheduling is further performed, a disorder degree can be lowered; the instruction scheduling efficiency is further increased; the overall performance of the ME is further improved.

Description

technical field [0001] The invention relates to network processor technology, in particular to an instruction scheduling method and device. Background technique [0002] In order to meet the needs of future network development and improve the performance of routers, the core routers at the backbone of the Internet (Internet) have undergone technological changes one after another. Especially in the high-end router market, the network processor has become an irreplaceable part of the routing and forwarding engine due to its outstanding packet processing performance and programmability. [0003] In the network processor system, the micro engine (ME, MicroEngine) is the core component of the network processor, and is responsible for completing the parsing and processing of the message according to the microcode instruction (MicrocodeInstructions). Microcode instructions are a necessary condition for ME to work. Therefore, ME instruction fetching and instruction scheduling affec...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/38
Inventor 周峰安康王志忠刘衡祁
Owner SANECHIPS TECH CO LTD
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