Semiconductor device
A semiconductor and device technology, applied in the field of semiconductor devices, can solve the problems of increased parasitic capacitance, non-negligible delay degradation, and increased height, and achieve the effect of preventing malfunctions
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no. 1 example
[0056] figure 1 is a block diagram showing a configuration example of a DRAM (semiconductor device) 11 according to the first embodiment. In the DRAM 11, peripheral circuits adjacent to the memory cell array region include signal lines supplied with a fixed potential and adjacent to the lower electrodes of the capacitive elements of the memory cells in the horizontal direction. This configuration enables the DRAM 11 to reduce the influence of noise from peripheral circuits and prevent malfunctions from occurring. This configuration will be described in detail below.
[0057] Such as figure 1 As shown, the DRAM 11 includes a memory cell array 111 , a word line driver 112 , a sense amplifier unit 116 , a selection circuit 113 , a data read unit 114 and a data write unit 115 . Metal lines LX and LY are disposed to surround the memory cell array 111 .
[0058] figure 2 is a plan view showing a detailed configuration of the memory cell array 111 .
[0059] refer to figure ...
no. 2 example
[0112] The DRAM 11 a according to the second embodiment includes a memory cell array 111 a instead of the memory cell array 111 . Figure 10 is a plan view showing the memory cell array 111a. Unlike the memory cell array 111, the memory cell array 111a does not include a plurality of dummy memory cells DMC surrounding the memory cells MC. Other constituents of the memory cell array 111a are similar to those of the memory cell array 111, and thus descriptions thereof are omitted.
[0113] First, the mechanism of noise transmission from the metal lines LX and LY to the memory cell MC will be described. Figure 11 It is a circuit diagram showing a memory cell MC provided on the outermost periphery of the memory cell array 111a, and a metal line (hereinafter also referred to as a “signal line”) LX or LY provided parallel to and adjacent to the memory cell MC.
[0114] Such as Figure 11 As shown, the signal line LX or LY is connected to the storage node ND of the memory cell MC...
no. 3 example
[0123] Compared with the DRAM 11 including the metal lines LX and LY supplied with a fixed potential, a method for setting the potential to be supplied to the dummy memory cell DMC is devised in the DRAM 11b according to the third embodiment.
[0124] Figure 13 is a block diagram showing the DRAM 11b.
[0125] Such as Figure 13 As shown, in the DRAM 11b, a power supply circuit for generating a potential to be supplied to the dummy memory cell DMC is provided separately from a power supply circuit for generating a potential for driving the memory cell MC. In this embodiment, as a representative of a plurality of power supply circuits that generate different potentials, only a power supply circuit for generating the potential VKK is shown.
[0126] Specifically, in the DRAM 11b, the power supply circuits 13 and 14 are provided outside the DRAM 11b. The power supply circuit 13 supplies a potential VKK to the dummy word line DWL. The power supply circuit 14 supplies a potent...
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