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Manufacturing method for inner lead lamination layer of semiconductor framework

A technology of lead wires and manufacturing methods in the frame, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as poor bonding force, product electrical parameters, functional failure, and easy to produce sticking molds.

Inactive Publication Date: 2016-09-07
泰兴市永志电子器件有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The bonding force between the silver-plated area with too many leads in the frame and the encapsulating plastic compound is relatively poor. In addition, the ductility of copper wire is much worse than that of gold wire. The internal temperature of power devices during reliability tests or during operation Higher, sometimes coupled with the harsh external environment, the interface between the silver-plated area of ​​the lead wire in the frame and the encapsulating plastic compound is prone to delamination, and the delamination is easy to pull the copper wire with poor ductility at the neck of the second solder joint. Cracks or breakage, resulting in failure of electrical parameters and functions of the product
In response to this failure, although the industry uses high-adhesive plastic molding compound to make the layering of the silver-plated area of ​​the lead wires in the frame, the cost of the molding compound is relatively high, and mold sticking is prone to occur during the molding operation, so the mold cleaning cycle has to be reduced However, the cost of mold cleaning is increased, so there is currently no economical and reliable practical method for the layered production between the silver-plated layer of the second soldering point of the copper wire and the encapsulating plastic compound.

Method used

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  • Manufacturing method for inner lead lamination layer of semiconductor framework
  • Manufacturing method for inner lead lamination layer of semiconductor framework
  • Manufacturing method for inner lead lamination layer of semiconductor framework

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Embodiment Construction

[0015] Embodiments of the present invention will be described below with reference to the drawings. Elements and features described in one drawing or one embodiment of the present invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that representation and description of components and processes that are not related to the present invention and known to those of ordinary skill in the art are omitted from the drawings and descriptions for the purpose of clarity.

[0016] Such as image 3 As shown, in the layered manufacturing method of the lead in the semiconductor frame provided by the embodiment of the present invention, the exposed copper surface is formed into a rough surface 2 in the welding area of ​​the lead 1 in the frame; a through hole 3 is arranged in the middle of the rough surface 2; On the right side, an ultra-narrow and ultra-thin silver plating layer 4 is formed through a special barrel pl...

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Abstract

The invention provides a manufacturing method for an inner lead lamination layer of a semiconductor framework. A through hole is formed in the copper-exposing surface of the inner lead of the framework; and an ultra-narrow and ultra-thin silver-plated region is plated on the two sides or on one side of the through hole in a rolling wheel manner. The through hole can reinforce the tightening and locking between the front and back surfaces of the inner lead of the framework and the encapsulating and plastic packaging material; the rolling wheel type electroplating process adopted by the ultra-narrow and ultra-thin silver-plated region greatly breaks through the technical index of the existing electroplating process, so that the silver-plated region can be greatly reduced, and the copper-exposing surface region of the inner lead of the framework can be increased to the maximum degree.

Description

technical field [0001] The invention relates to the technical field of manufacturing frames used in semiconductor devices, in particular to a layered manufacturing method for inner leads of semiconductor frames. Background technique [0002] In the packaging process of semiconductor power devices, the chip carrier of the frame is mainly used to accept the chip, and the chip is fixed on the surface of the chip carrier by a high thermal conductivity alloy material, so that the effective conduction of heat and electricity between the frame carrier and the chip is realized. The lead in the frame is used as the second welding point area where the copper wire is drawn out on the chip, so that effective electrical conduction can be realized between the chip and the lead in the frame, so as to meet the packaging requirements of the power device. After copper wire bonding as figure 1 As shown, it includes: a frame stage 3 for heat dissipation and carrying chips 4; a high thermal con...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/48H01L23/495
CPCH01L23/49582H01L21/4821H01L23/49541H01L2224/48247H01L2224/49111H01L2224/73265
Inventor 熊志
Owner 泰兴市永志电子器件有限公司