Quick clock stretching circuit of simplified structure

Abstract

The invention discloses a quick clock stretching circuit of a simplified structure, and the circuit consists of a phase clock generation module, a clock synchronization selection module, and a control module. The phase clock generation module obtains phase clocks of different phases through a time delay unit. The control module generates a control signal according to an external stretching enabling signal and a configurable stretching scale signal, and carries out the synchronization processing of the control signal, so as to finally select a target stretching clock, and achieve the quick and accurate stretching of a system clock in one period. The circuit is simple in structure, is simple in implementation, does not need complex gate devices, is smaller in area and power consumption cost, obtains the area cost at a certain precision cost, and is especially suitable for an adaptive voltage frequency adjustment circuit based on online time sequence monitoring.

Description

technical field [0001] The invention relates to a fast clock stretching circuit with simplified structure, which is realized by digital logic and belongs to the field of integrated circuit design. technical background [0002] In recent years, integrated circuits (Integrated Circuit, IC) have continued to develop, and the number of transistors in chips has continued to increase according to Moore's Law, making chip power consumption an important issue that cannot be ignored in chip design. Therefore, various low-power consumption technologies have emerged as the times require. [0003] In recent years, wide voltage (Wide voltage range) integrated circuits have received widespread attention. It usually covers the near / sub-threshold region to the conventional voltage region, and the operating voltage of the chip can be changed within a wide voltage range to meet different loads of the chip. Under the high performance or high energy efficiency requirements. However, due to the...

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Problems solved by technology

The method of frequency division can achieve immediate frequency reduction, but because only integer multiple frequency division can be achieved (usually using two frequency division), the chip frequency is greatly reduced, and the chip's working performance is also reduced; while the method of using PLL dynamic configuration Although a relatively small frequency adjustment can be achieved, it is not suitable for fast frequency adjustment due to the stabilization time required for PLL adjustment

The published clock stretching circuit has a complex structure, and usually uses multiple DLLs (Delay-Locked Loop) to realize multi-phase clock generation. The delay phase control is relatively accurate, but the area overhead is relatively large, and it is not suitable for embedded low-power chips.

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