Test system and method for fpga chip embedded bram core

Abstract

The invention belongs to the technical field of integrated circuits and discloses a chip inner partial reconfiguration-based test system and method of a BRAM core embedded in a field programmable gate array (FPGA) chip. The test system comprises a TPG module, an ORA module, a PR_BRAM module, a BUF module, a chip inner reconfiguration control module and a bit stream storage module. The system and method utilizes a partial reconfiguration function of FPGA and a chip inner configuration port to finish inner automatic partial reconfiguration so that a test of an embedded BRAM core is realized. The system and method improve a test algorithm, improves a fault-coverage rate, improves coverage on a writing destroying fault, a reading destroying fault, an interference coupling fault, a writing destroying coupling fault, a reading destroying coupling fault and a BRAM initialization function fault based on the existing method, and utilizes the FPGA chip inner configuration port to realize chip inner automatic partial reconfiguration of the test algorithm so that the test configuration number is reduced and test time is reduced.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a test system and method for a BRAM core embedded in an FPGA chip. Background technique [0002] With the development of integrated circuits, while the Field Programmable Gate Array (FPGA) is continuously expanding the programmable logic array, the scale of various embedded programmable intellectual property (IP) cores is also continuously expanding, making the performance of FPGA Getting stronger and stronger. Therefore, how to efficiently and comprehensively test the programmable logic array and IP core of the chip has become a major issue. As the BRAM core is one of the most commonly used IP cores in the FPGA, how to test the correctness of its functions is particularly important. In chip testing, test time and test coverage are the two most important indicators, which directly reflect the effectiveness of chip testing. For the test of FPGA chips, du...

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Problems solved by technology

as in literature [5] In , the March LR algorithm is used when covering SRAM faults [6] , can cover address decoding faults, stuck faults, open circuit faults, conversion faults, coupling faults (including all inversion coupling faults, equal power coupling faults, state coupling faults and some interference coupling faults), and also increase the number of configurations to cover The dual-port read and write function of BRAM, multiple bit width modes, cascade function, ECC function and FIFO function and other possible faults have been eliminated, and the fault coverage rate is relatively high. In the end, a total of 5 complete configurations were used, supplemented by 14 partial configurations. The test of Xilinx Virtex-5 FPGA is completed, but there are still faults not covered, such as write corruption faults, read corruption faults and partial coupling faults in SRAM faults, initialization function faults in BRAM functions have not been tested, and still There are too many test configurations and long test time

while in the literature [7] In the method adopted in the paper, the improved March C-algorithm is used. Although only one complete configuration is used to complete the test of the Virtex-4 series FPGA embedded BRAM, it can only detect part of the SRAM failure, and the other functions of the BRAM For example, dual-port read and write functions, multiple bit width modes, cascade functions, ECC functions, FIFO functions, and initialization functions have not been tested, so the fault coverage of the test is low

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