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Manufacturing method for silicon waveguide

A fabrication method and technology of silicon waveguide, which are applied in the field of integrated optics and microelectronics, can solve the problem that the roughness of the sidewall cannot meet the usage requirements, and achieve the effects of improving the morphology of the sidewall and reducing the scattering loss and transmission loss.

Active Publication Date: 2016-11-09
CHINA ELECTRONICS TECH GRP NO 23 RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the starting point of the above improvement methods is to directly focus on the improvement of surface roughness, which requires continuous improvement in technology, and the improved side wall roughness still cannot meet the needs of use.

Method used

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  • Manufacturing method for silicon waveguide
  • Manufacturing method for silicon waveguide
  • Manufacturing method for silicon waveguide

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Experimental program
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Effect test

Embodiment 1

[0031] The specific process steps of the silicon waveguide manufacturing method are as follows:

[0032] S1: Deposit a mask layer 31 on the surface of the silicon substrate 21 to obtain a silicon wafer 22; the mask layer 31 is preferably a silicon oxide layer; the silicon oxide layer is deposited by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition deposited on the silicon substrate 21 by product method PECVD or thermal oxidation method; as Figure 6 shown.

[0033] S2: A photoresist plate processed by silicon waveguide grooves is used to form a photoresist window 32 on the surface of the mask layer 31 by a photolithography process, and the remaining photoresist on the surface is removed after the first etching; Figure 7 shown.

[0034] S3: The dry plasma etching process is used for the second etching. The etching depth is X+Y. The X value is determined according to the needs, usually greater than 1um. For example, the X value is 1....

Embodiment 2

[0038] The specific process steps of the silicon waveguide manufacturing method are as follows:

[0039] S1: Deposit a mask layer 31 on the surface of the silicon substrate 21 to obtain a silicon wafer 22; the mask layer 31 is preferably a silicon oxide layer; the silicon oxide layer is deposited by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition deposited on the silicon substrate 21 by product method PECVD or thermal oxidation method; as Figure 6 shown.

[0040] S2: A photoresist plate processed by silicon waveguide grooves is used to form a photoresist window 32 on the surface of the mask layer 31 by a photolithography process, and the remaining photoresist on the surface is removed after the first etching; Figure 7 shown.

[0041] S3: The dry plasma etching process is used for the second etching. The etching depth is X+Y. The X value is determined according to the needs, usually a depth greater than 1um. For example, the X val...

Embodiment 3

[0045] The specific process steps of the silicon waveguide manufacturing method are as follows:

[0046] S1: Deposit a mask layer 31 on the surface of the silicon substrate 21 to obtain a silicon wafer 22; the mask layer 31 is preferably a silicon nitride layer; the silicon nitride layer is deposited by low-pressure chemical vapor deposition method LPCVD or plasma enhanced chemical Vapor deposition method PECVD is deposited on described silicon substrate 21; Figure 6 shown.

[0047] S2: A photoresist plate processed with a silicon waveguide groove is used to form a photoresist window 32 on the surface of the mask layer 31 by a photolithography process, and the photoresist remaining on the surface is removed after the first etching; Figure 7 shown.

[0048] S3: The dry plasma etching process is used for the second etching. The etching depth is X+Y. The X value is determined according to the needs, usually a depth greater than 1um. For example, the X value is 2.5um, and the ...

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Abstract

The invention discloses a manufacturing method for a silicon waveguide. The manufacturing method comprises the steps of S1, depositing a mask layer on the surface of a silicon substrate, wherein the mask layer is a silicon oxide layer or a silicon nitride layer; S2, forming a photoresist window in the surface of the mask layer by utilizing a photolithography which is processed by a silicon waveguide trench through a photolithographic process, and removing the residual photoresist from the surface after the etching for the first time is implemented; S3, performing etching for the second time by a dry method plasma etching process at the etching depth of X+Y, and removing the residual mask layer after etching, wherein X is the etching depth required by the silicon waveguide, and Y is extra loss depth; and S4, removing the silicon layer with the thickness Y by a planarization process to obtain the required silicon trench. By adoption of the manufacturing method, the side wall roughness degree of the silicon trench can be greatly reduced on the level of the existing etching process, so that the transmission loss of the silicon-based optical waveguide can be lowered.

Description

technical field [0001] The invention belongs to the field of integrated optics and microelectronics, and relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a silicon waveguide. Background technique [0002] In the manufacture of semiconductor integrated circuits, the formation of silicon-based waveguides is generally obtained by etching the silicon substrate. Glue is used as a shield to etch the silicon trench shielding layer, and then the photoresist is removed, and then silicon trenches with required depth and sidewall angle are etched, and finally the shielding layer is removed. [0003] In the actual production process, due to the verticality requirement of waveguide etching, dry plasma etching is required for etching. Streaks in the straight direction (usually called "striation", in the present invention, the side wall with such striations is called "rough side wall", and the severity of such striations...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/302H01L21/3065H01P11/00
CPCH01L21/302H01L21/3065H01P11/001
Inventor 李冰姜剑光陈东石
Owner CHINA ELECTRONICS TECH GRP NO 23 RES INST
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