Groove power device and manufacturing method therefor

Abstract

The invention discloses a groove power device and a manufacturing method therefor. A gate electrode material layer in a groove has a part which is higher than a second stop layer, and the part is oxidized to generate a second oxide layer; a part of the second stop layer is covered with the second oxide layer; then a side wall is formed, so that the overall groove-gate structure is protected; under a condition of the existing photoetching equipment, the groove-gate structure is not affected by an unstable process of a contact hole in a processing technology; therefore, the production of products with smaller linewidth and higher alignment margin is realized; and the parameters and reliability of the products can satisfy the requirement.

Description

technical field [0001] The invention relates to the field of semiconductor equipment, in particular to a trench power device and a manufacturing method. Background technique [0002] Power devices can be divided into power IC (integrated circuit) devices and power discrete devices. Power discrete devices include power MOSFETs (metal-oxide semiconductor field effect transistors), high-power transistors and IGBTs (insulated gate bipolar transistors). and other devices. Early power devices were produced based on planar technology, but with the development of semiconductor technology, small size, high power, and high performance have become the main development trend. Taking the planar process MOSFET device as an example, due to the limitation of the parasitic resistance of the JFET (junction field effect transistor) in its own body, the area of ​​a single cell is limited, which makes it difficult to increase the density of the cell, and it is difficult to make the planar The ...

AI Technical Summary

Problems solved by technology

This is a typical failure situation where the line width is too large and the equipment capacity cannot meet the smaller size processing of the product

[0006] Area C represents the structure where the lithographic line width of the contact hole 4 meets the small line width requirements, but the overlay capability of the lithography equipment cannot meet the product structure requirements, and finally the contact hole 4 is not in the middle of the left and right trenches 5, resulting in abnormal parameters. appearance

At this time, the line width of the contact hole 4 formed on the surface of the semiconductor substrate 1 is d3, and the distances between the contact hole 4 and the adjacent trench 5 are c1 and c2 respectively, wherein c1 is much larger than the misalignment margin range of the product design, c2 is also smaller than the misalignment margin range of the product design, and even the contact hole 4 is infinitely close to the gate oxide 3 and polysilicon 2 in the trench 5, and it is also prone to parameter abnormalities such as Vth, BVds, Rdson, and even GS short circuit.

This is a typical failure situation where the line width capability of the lithography equipment is normal but the overlay accuracy cannot meet the smaller size of the product

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