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Method for passivating high-k/Ge interface by ozone while improving high-k gate dielectric

A technology of ozone passivation and gate dielectric, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of thick GeO2, unstable properties, and easy water reaction, etc. The effect of improving the effect and avoiding the effect of pollution

Inactive Publication Date: 2016-11-23
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

However, GeO 2 Unstable in nature, easy to react with water when exposed to air, in addition, it starts thermal analysis when the temperature exceeds 400°C
Traditionally, thermal oxidation is used to form GeO 2 , although an excellent interface can be obtained, the oxidation temperature is required to be high (over 500°C), and the GeO produced 2 Thick thickness is not conducive to the reduction of EOT

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  • Method for passivating high-k/Ge interface by ozone while improving high-k gate dielectric
  • Method for passivating high-k/Ge interface by ozone while improving high-k gate dielectric
  • Method for passivating high-k/Ge interface by ozone while improving high-k gate dielectric

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Embodiment Construction

[0026] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0027] The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and / or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicat...

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Abstract

The invention provides a method for passivating a high-k / Ge interface by ozone while improving a high-k gate dielectric. The method comprises the steps of: providing a substrate, wherein the substrate is a Ge substrate or a wafer containing a Ge thin film surface; carrying out high-k gate dielectric growing and ozone treatment on the substrate alternately, and forming a high-k / GeOx / Ge gate stack structure on the substrate; and performing low-temperature oxygen annealing on the high-k gate dielectric to enhance quality of the high-k gate dielectric. By adopting the method for passivating the high-k / Ge interface by ozone while improving the high-k gate dielectric, the ultrathin GeOx layer is formed on the Ge surface, further the EOT is reduced, the quality of the high-k / Ge interface is improved, and good high-k / Ge interface passivation effect is achieved.

Description

technical field [0001] The invention relates to semiconductor manufacturing technology, in particular to a manufacturing method for ozone passivation of high-k / Ge interface and improvement of high-k gate dielectric. Background technique [0002] As the core and foundation of the information industry, semiconductor technology is an important symbol to measure a country's scientific and technological progress and comprehensive national strength. In the past 40 years, silicon-based integration technology has followed Moore's law to increase the working speed of devices, increase integration and reduce costs by reducing the feature size of devices. The feature size of silicon-based CMOS devices has been reduced from micrometers to nanometers. However, when the gate length of the device is reduced to less than 90nm, the thickness of the gate dielectric (silicon dioxide) has been gradually reduced to close to 1nm, and physical limitations such as increased off-state leakage, incre...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28
CPCH01L21/28211
Inventor 刘洪刚杨旭王盛凯龚著靖孙兵常虎东赵威
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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