A neural network processor, design method, and chip based on data compression

Abstract

The present invention proposes a neural network processor, design method and chip based on data compression. The processor includes at least one storage unit for storing operation instructions and data participating in calculations; at least one storage unit controller for all The storage unit performs control; at least one computing unit is used to perform computing operations of the neural network; a control unit is connected to the storage unit controller and the computing unit, and is used to obtain the storage via the storage unit controller The unit stores instructions, and parses the instructions to control the computing unit; at least one data compression unit is used to compress the data participating in the calculation according to the data compression storage format, wherein each of the data compression units is related to the data compression unit. The computing units are connected. The invention reduces the occupation of data resources in the neural network processor, increases the computing speed, and improves energy efficiency.

Description

technical field [0001] The invention relates to the field of hardware acceleration for neural network model calculation, in particular to a data compression-based neural network processor, design method and chip. Background technique [0002] Deep learning technology has developed rapidly in recent years. Deep neural networks, especially convolutional neural networks, have achieved a wide range of applications in image recognition, speech recognition, natural language understanding, weather prediction, gene expression, content recommendation, and intelligent robots. [0003] The deep network structure obtained by deep learning is an operational model, which contains a large number of data nodes, each data node is connected to other data nodes, and the connection relationship between each node is represented by weight. With the continuous improvement of the complexity of the neural network, the neural network technology has many problems in the actual application process, su...

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Literature "Albericio J, Judd P, Hetherington T, et al.Cnvlutin: ineffective-neuron-free deep neural network computing[C] / / Computer Architecture(ISCA),2016ACM / IEEE 43rd Annual International Symposium on.IEEE,2016:1 -13." By providing large-scale storage units on the chip to achieve large-scale parallel computing and based on this, the compression of data elements is realized, but this method relies on large-scale on-chip storage units to meet its parallel computing needs, Not suitable for embedded devices; "Chen Y H, Emer J, Sze V.Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks[J].2016." Data reuse and power by sharing data and weights The gating method closes the calculation of data 0, which can effectively improve energy efficiency, but this method can only reduce the power consumption of the operation and cannot skip elements with a value of 0 to speed up the calculation.

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