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Semiconductor device and manufacturing method thereof, and electronic device

A manufacturing method and semiconductor technology, which is applied in semiconductor/solid-state device manufacturing, circuits, transistors, etc., can solve the problems of interlayer dielectric gate spacer damage and residue, so as to avoid interlayer dielectric damage and improve yield and performance , the effect of high interface performance

Active Publication Date: 2017-04-26
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But when the dummy gate oxide is removed, the interlayer dielectric (ILD) and gate spacer will be damaged, and when the high-k material and the metal gate are deposited, and due to this damage in the metal gate planarization (CMP) left behind

Method used

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  • Semiconductor device and manufacturing method thereof, and electronic device
  • Semiconductor device and manufacturing method thereof, and electronic device
  • Semiconductor device and manufacturing method thereof, and electronic device

Examples

Experimental program
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Effect test

Embodiment 1

[0033] The following will refer to figure 1 as well as Figure 2A ~ Figure 2C The manufacturing method of the semiconductor device of the present invention is described in detail.

[0034] First, step S101 is performed to provide a semiconductor substrate on which a contact etch stop layer is formed.

[0035] Such as Figure 2A As shown, a semiconductor substrate 200 is provided on which a contact etch stop layer 201 is formed.

[0036] Wherein, the semiconductor substrate 200 can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also includes multiple semiconductors composed of these semiconductors. Layer structure, etc., or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI) and germanium-on-insulator (GeOI), etc. In this embodiment, the constituent material of the semiconductor substrate 200 is sele...

Embodiment 2

[0048] The present invention also provides a semiconductor device manufactured by the method described in Embodiment 1, which includes: a semiconductor substrate 300, a contact etch stop layer and an interlayer dielectric 307 formed on the semiconductor substrate 300, the The contact etch stop layer includes a bottom layer 305 and a surface layer 306 having high interfacial properties through a process. The contact etch stop layer bottom layer 305 is nitride, such as silicon nitride, and the contact etch stop surface layer 306 is oxide, such as silicon dioxide. Preferably, the contact etch stop surface layer 306 is dense oxide. The interlayer dielectric 307 is a low-K or ultra-low-K material, or a porous low-K material, such as SiCOH or porous SiCOH.

[0049] Wherein, the semiconductor substrate 300 can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also includes multiple semiconductors c...

Embodiment 3

[0053] The present invention further provides an electronic device including the aforementioned semiconductor device.

[0054] The electronic device also has the above-mentioned advantages due to the higher performance of the included semiconductor devices.

[0055] The electronic device can be any electronic product or equipment such as mobile phone, tablet computer, notebook computer, netbook, game console, TV, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP, etc. It is an intermediate product with the above-mentioned semiconductor device, for example: a mobile phone motherboard with the integrated circuit, etc.

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PUM

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Abstract

The invention relates to a semiconductor device, a manufacturing method thereof, and an electronic device. The manufacturing method comprises the step of: providing a semiconductor substrate, and forming a contact etching stop layer on the semiconductor substrate; forming an interlayer dielectric on the contact etching stop layer; and executing a treatment process on the surface layer of the contact etching stop layer before the formation of the interlayer dielectric, so as to improve interface performance of the surface layer of the contact etching stop layer. By adopting the manufacturing method of the semiconductor device provided by the invention, the interface performance of the surface layer of the contact etching stop layer is improved since the treatment process is executed on the surface layer of the contact etching stop layer, thus the interlayer dielectric formed subsequently is closely combined with the contact etching stop layer, thereby being capable of avoiding problems of damage to the interlayer dielectric caused by the subsequent removal of a virtual gate and the existence of residues after metal gate planarization.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] With the development of semiconductor technology, the geometric size of CMOS (complementary metal oxide) devices in large-scale integrated circuits has been continuously reduced, and the feature size of semiconductor devices has been reduced to the nanometer level. Using traditional SiO 2 When making the gate oxide layer, the leakage current is getting bigger and bigger. Various improvement technologies have been proposed, such as the use of high-K gate dielectric materials and metal gates. At the same time, in order to avoid the impact of high-temperature processes on the technology gate, for the 20nm technology node, High-K last and metal gate last processes are preferred. [0003] In addition, with the shrinking of CMOS devices, in order to meet the d...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238H01L21/3105H01L21/318H01L27/092
CPCH01L27/092H01L21/0223H01L21/02252H01L21/3105H01L21/8238
Inventor 禹国宾
Owner SEMICON MFG INT (SHANGHAI) CORP