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Back metallization structure and processing technology of silicon wafer for eutectic bonding

A backside metallization and eutectic welding technology, applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve problems such as poor eutectic, chip peeling, tin layer oxidation, etc., to achieve large coverage and increase reliability. Sex, reducing the effect of toxic effects

Active Publication Date: 2019-02-26
爱特微(张家港)半导体技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The existing three-layer low-temperature tin eutectic is prone to oxidation of the tin layer during storage, and problems such as poor eutectic, virtual soldering, less residue, and overheating during wave soldering that cause the chip to fall off in the later stage of packaging.

Method used

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  • Back metallization structure and processing technology of silicon wafer for eutectic bonding

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0028] 1. Metallized structure

[0029] The backside metallization structure of the eutectic silicon chip of the present embodiment comprises the first metal layer 2 made of titanium, the second metal layer 3 made of nickel, the third metal layer 4 made of silver, and the material made of tin copper The fourth metal layer 5 of alloy and the fifth metal layer 6 made of silver.

[0030] 2. The processing steps are:

[0031] (1) prepare tin-copper alloy, the percentage by weight of tin in the tin-copper alloy is 60%, and the percentage by weight of copper is 40%;

[0032] (2) Carry out film-sticking process to the front of silicon wafer 1, then carry out film-repair inspection to the edge;

[0033] (3) thinning the back substrate of the silicon wafer 1, after processing, remove the film on the front side;

[0034] (4) silicon wafer 1 is cleaned;

[0035] (5) Put the silicon wafer 1 into the evaporation furnace after cleaning;

[0036] (6) Carry out evaporation treatment to t...

Embodiment 2

[0039] 1. Metallized structure

[0040] The back metallization structure of the eutectic silicon chip of the present embodiment comprises the first metal layer 2 made of vanadium, the second metal layer 3 made of nickel, the third metal layer 4 made of silver, and the material made of tin copper The fourth metal layer 5 made of alloy or tin-antimony alloy and the fifth metal layer 6 made of silver.

[0041] 2. The processing steps are:

[0042] (1) prepare tin-antimony alloy, the percentage by weight of tin is 92% in the alloy of tin-antimony, and the percentage by weight of antimony is 8%;

[0043] (2) Carry out film-sticking process to the front of silicon wafer 1, then carry out film-repair inspection to the edge;

[0044] (3) thinning the back substrate of the silicon wafer 1, after processing, remove the film on the front side;

[0045] (4) silicon wafer 1 is cleaned;

[0046] (5) Put the silicon wafer 1 into the evaporation furnace after cleaning;

[0047] (6) Carry...

Embodiment 3

[0050] 1. Metallized structure

[0051] The backside metallization structure of the eutectic silicon wafer of the present embodiment comprises the first metal layer 2 made of chromium, the second metal layer 3 made of nickel, the third metal layer 4 made of silver, and the material made of tin copper The fourth metal layer 5 of alloy and the fifth metal layer 6 made of silver.

[0052] 2. The processing steps are:

[0053] (1) prepare tin-copper alloy, the percentage by weight of tin in the tin-copper alloy is 65%, and the percentage by weight of copper is 35%;

[0054] (2) Carry out film-sticking process to the front of silicon wafer 1, then carry out film-repair inspection to the edge;

[0055] (3) thinning the back substrate of the silicon wafer 1, after processing, remove the film on the front side;

[0056](4) silicon wafer 1 is cleaned;

[0057] (5) Put the silicon wafer 1 into the evaporation furnace after cleaning;

[0058] (6) Carry out evaporation treatment to t...

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Abstract

The invention belongs to the technical field of semiconductor, and specifically relates to a silicon wafer back metallization structure for eutectic bonding and a processing technology. The surface of a back substrate silicon wafer is plated with a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer in sequence from the near to the distant relative to the silicon wafer, wherein the first metal layer is made of titanium, vanadium or chromium, the second metal layer is made of nickel, the third metal layer is made of silver, the fourth metal layer is made of tin-copper or tin-antimony alloy, and the fifth metal layer is made of silver. According the silicon wafer back metallization structure for eutectic bonding and the processing technology of the invention, the cost is reduced under the condition of no toxicity, phenomena such as bad eutectic performance and pseudo soldering are avoided during packaging, and over temperature is avoided during wave soldering. The silicon wafer back metallization structure for eutectic bonding and processing technology have higher reliability, large coverage and a wide range of applications.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a backside metallization structure and processing technology of a silicon chip for eutectic welding. Background technique [0002] Eutectic welding is also called low melting point alloy welding. The basic characteristic of eutectic alloys is that two different metals can be alloyed in a certain weight ratio at a temperature far below their respective melting points. The most commonly used eutectic bonding in microelectronic devices is to solder the silicon chip to the gold-plated base or lead frame, that is, "gold-silicon eutectic bonding". The current gold-arsenic eutectic process is costly and toxic. The existing three-layer low-temperature tin eutectic is prone to oxidation of the tin layer during storage, and problems such as poor eutectic, virtual soldering, little residue, and overheating during wave soldering that cause the chip to fall off in the lat...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/482H01L21/60
CPCH01L24/27H01L24/29H01L2224/2745H01L2224/28105H01L2224/2958
Inventor 王献兵
Owner 爱特微(张家港)半导体技术有限公司