Multilevel folding-interpolation type analog-digital converter and decoding method thereof

Abstract

The invention discloses a multilevel folding-interpolation type ADC (Analog-Digital Converter) and a decoding method thereof. The decoding method comprises the steps of, by a current-level decoding structure, carrying out folding-interpolation on a folding curve of an upper-level decoding structure and multiplying the output value of the upper-level decoding structure by odd times of weighting by utilizing a weight adder; summing the decoding result of the current-level decoding structure and the output value of the current-level weight adder by utilizing an inter-level adder; transmitting the summing result which is regarded as output value of the current-level decoding structure to the next-level decoding structure, wherein the output value of the last-level decoding structure is regarded as analog-digital conversion result. The decoding method utilizes a mode of a multilevel production line framework and adopts a production line form for decoding. Final quantification can be completed by adding results together after each level of decoding is multiplied by a corresponding weight, and then enabling the summing result to be subjected to the decimal-to-binary conversion logic. As the production line is utilized, the decoding cycle is saved, the complex degree of the decoding circuit can be simplified to the greatest extent, and the problem that the decoding is too difficult due to that an odd number cannot be simplified into a 2n form can be solved efficiently.

Description

technical field [0001] The invention relates to the technical field of integrated circuit data converter chips, in particular to a multi-stage folding and interpolation analog-to-digital converter and a decoding method thereof. Background technique [0002] The analog-to-digital converter (ADC) with folded interpolation structure has been widely used with fewer comparators, less area and less power consumption. However, if an ADC with a folded interpolation structure is to achieve high-precision quantization, a high fold rate is required. However, since the folded parallel signal needs a sufficient voltage range to ensure that only one pair of differential pairs is activated each time, and the others are in the saturation region, the folding rate of the single-stage folding circuit cannot be too high. In addition, the speed of the circuit is reduced due to the large load due to the high folding rate of the single stage. Therefore, when a high-precision ADC is implemented w...

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Problems solved by technology

[0004] In order to solve the above problems, the present invention provides a multi-level folding and interpolation analog-to-digital converter and its decoding method, which can realize 10-12bit quantization, and is used to solve the problem that the traditional odd-numbered folding rate decoding algorithm is too complicated

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