Photolithography solution prediction method based on layout geometric feature matching

A solution and geometric feature technology, applied in the field of lithography solution prediction based on layout geometric feature matching, can solve problems such as inability to intuitively feedback layout design, inability to analyze unknown or undetected, and inability to provide unknown layout graphics, etc. Achieve the effect of shortening the development cycle, ensuring successful implementation, and reducing selection time
CN106773541AActive Publication Date: 2017-05-31INST OF MICROELECTRONICS CHINESE ACAD OF SCI +1
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
Publication Date
2017-05-31

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Abstract

The invention belongs to the field of the semiconductor manufacturing technology, and discloses a photolithography solution prediction method based on layout geometric feature matching. The method includes the following steps that a standard layout geometric information database is obtained, to-be-matched layout geometric information is obtained, geometric information in the to-be-matched layout geometric information and geometric information in the standard layout geometric information database are matched, according to the matching result, a first standard layout is selected, a photolithography solution corresponding to the first standard layout serves as a photolithography solution candidate of a to-be-matched layout, and the photolithography solution of the to-be-matched layout is predicted. The method solves the problems that in the prior art, a unknown or untested geometric figure combination can not be analyzed, a pre-selected solution obtained by technological research and development can not be provided for an unknown layout graph, and the defects of the layout design can not be directly fed back. The method achieves the technical effects of providing a pre-selected solution obtained by technological research and development for the unknown layout graph, and the defects of the layout design are directly fed back.
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Description

technical field

[0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a lithography solution prediction method based on layout geometric feature matching. Background technique

[0002] With the improvement of semiconductor technology level and the growth of market demand, the complexity of very large scale integration (VLSI) design is getting higher and higher, and there are some unexpected adverse interactions between design layout and production process flow. Process imperfections lead to highly variable layout geometry feature sizes, making these interactions very difficult to predict. Ideally, a physical design layout verification step should be able to capture potential process defect-prone geometries in the layout.

[0003] The function of traditional design rule checking (DRC) is based on a large number of pre-set fixed geometric size combination rules. By checking whether the graphic structure meets the requirements of ...

Claims

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