LDPC encoder with two-stage partial parallel inputting accumulation left shift in DTMB

Abstract

The invention provides a QC-LDPC encoder based on two-stage assembly line in DTMB. The encoder comprises a sparse-matrix-and-vector multiplier and a vector-and-high-density-matrix multiplier. The sparse-matrix-and-vector multiplier is used for realizing multiplication of a sparse matrix and a vector; and the vector-and-high-density-matrix multiplier employs a partial parallel inputting accumulation left shift mechanism to realize multiplication of a vector and a high-density matrix. The whole encoding process is divided into two stages of assembly lines. The QC-LDPC encoder with the four-fifth code rate has advantages of low cost and high handling capacity.

Description

technical field [0001] The invention relates to the field of channel coding, in particular to a QC-LDPC coder with two-stage partial parallel input accumulation left shift in DTMB system. Background technique [0002] Low-Density Parity-Check (Low-Density Parity-Check, LDPC) code is one of efficient channel coding techniques, and Quasi-Cyclic LDPC (QC-LDPC) code is a special LDPC code. Both the generation matrix G and the check matrix H of the QC-LDPC code are arrays composed of circulant matrices, which have the characteristics of a segmented cycle, so they are called QC-LDPC codes. The first row of the circulant matrix is ​​the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the previous row by 1 bit. Therefore, the circulant matrix is ​​completely characterized by its first row. Usually, the first row of a circulant matrix is ​​called its generator polynomial. [0003] The DTMB standard adopts...

AI Technical Summary

Problems solved by technology

This scheme has two disadvantages: one is that a large amount of memory is required, resulting in high circuit cost; the other is that the information bits are serially input, and the encoding speed is slow

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