3D NAND memory device and manufacturing method therefor
A technology for storage devices and storage areas, which is applied in the field of flash memory, can solve the problems of increased numbers and the inability to integrate 3D NAND devices together, and achieve the effect of easy process integration
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[0059] Example one
[0060] reference figure 1 As shown, it is a schematic top view of a 3D NAND memory device chip according to an embodiment of the present invention. In this specific embodiment, the memory chip includes 4 plate storage areas, in each plate storage area Contains multiple block storage areas. It can be understood that this is only an example, and other design arrangements can be provided according to different designs, and the present invention is not limited to this.
[0061] reference figure 2 Shown as figure 1 A partial enlarged view of the middle area 40, which shows a stepped structure and part of the first storage area. In the first storage area 10, one block is divided into three parts by gate line gaps, and each pair of gate line gaps There is a finger storage area in between. The first storage area is an array area of 3D NAND memory cells, which may include one or more block storage areas.
[0062] In this embodiment, the gate line gaps 46 of the stepp...
Example Embodiment
[0064] Example two
[0065] In this embodiment, different parts from the first embodiment will be described, and the same parts will not be repeated.
[0066] reference image 3 Shown as figure 1 A partial enlarged view of the middle area 40, which shows a stepped structure and part of the first storage area. In the first storage area 10, one block is divided into three parts by gate line gaps, and each pair of gate line gaps There is a finger storage area in between. The first storage area is an array area of 3D NAND memory cells, which may include one or more block storage areas.
[0067] The sub-step area 41 is disposed between the gate line gaps of the corresponding block area of the step structure 40, and the corresponding area of the step structure (not shown in the figure) on the other side is used for the formation of the interconnect structure. In other words, the sub-step area 41 occupies the step structure area corresponding to a block area of the first storage ar...
Example Embodiment
[0068] Example three
[0069] In addition, a through contact hole area can also be provided in the bit line direction for connection with the CMOS circuit chip. Refer to figure 1 with Figure 4 As shown, Figure 4 for figure 1 A partial enlarged view of the middle area 11, a through hole formation area 20 is provided between the first storage area 10 and the second storage area 30, and the first storage area 10, the through hole formation area 20 and the second storage area 30 are along the bit line Arranged in sequence, the same as the first storage area 10, the second storage area 20 includes a word line stacking layer and a channel hole 12 in the word line stacking layer; the through hole forming area 20 includes a through hole stack of an oxide layer and a nitride layer The layer 24, the through contact holes 26 passing through the via stack 24, and the insulating layer 22 on the sidewall of the via stack; the gate line gap 16 in the first storage area 10 and the second storag...
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