Non-volatile memory device having a gap in the tunnuel insulating layer and method of manufacturing the same

Abstract

A non- volatile memory device (1, 101, 201, 301) having a gap within a tunnel dielectric layer (14, 114, 214, 314) and a method of manufacturing the same is provided. The devices have a stack of layers on top of a substrate (10, 110, 210, 310) including, a charge tunneling layer with a gap (14, 114, 214, 314), a charge storage layer (16, 116, 216, 316), a control gate layer (20, 120, 220, 320) andan insulating layer (18, 118, 218 220) in between the charge storage layer and the control gate. Manufacturing proceeds through deposition of a sacrificial layer (28, 128,228,328) on parts of a substrate, whereupon a stack of layers (24, 124,224,324) including a charge-storage layer, an insulating layer and a control gate layer are formed. Subsequently, selected parts of the sacrificial layer areremoved, thereby forming a gap in between the charge storage region and the substrate. The gap is protected from future processing by deposition of a sealing layer (34, 134, 234, 334). Such a devicehas a reduced operating voltage and its manufacture can be easily implemented in existing semiconductor processes.

Description

technical field [0001] The present invention relates to non-volatile memory devices and devices including such devices. Such devices can be used as stand-alone or embedded non-volatile memory (NVM), such as electrically erasable programmable read-only memory (EEPROM) or flash memory. The invention also relates to methods of making such devices. Background technique [0002] A non-volatile memory device typically consists of a transistor device comprising a source region, a drain region and a channel between the drain and source regions formed in a silicon semiconductor substrate region, and a charge storage region (CSR) formed on the substrate between the channel region and a conductive control gate, usually made of highly doped polysilicon. The charge storage region is separated and insulated from the substrate by a tunnel dielectric layer and from the control gate by an insulating layer. [0003] In conventional devices, the CSR consists of a floating gate made of heavi...

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Problems solved by technology

However, this document does not disclose suitable low-k tunnel dielectric materials

Furthermore, the practical application of high-k materials has profound disadvantages, such as difficult and costly integration in semiconductor fabrication processes due to mismatch of material properties and contamination issues, resulting in reduced reliability of memory devices

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