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A 3D NAND memory device and its manufacturing method

A technology for storage devices and storage areas, which is applied in the direction of semiconductor devices, electric solid state devices, electrical components, etc., can solve the problems of increasing numbers and the inability to integrate 3D NAND devices together, and achieve the effect of easy process integration

Active Publication Date: 2018-11-30
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In the 3D NAND memory structure, the stacked 3D NAND memory structure is realized by stacking multiple layers of data storage units vertically. However, other circuits such as decoder, page buffer and latch ), etc., these peripheral circuits are all formed by CMOS devices, and the technology of CMOS devices cannot be integrated with 3D NAND devices. An array of vias electrically connects the two together
The stacking in the 3D NAND memory array mainly adopts the OPOP structure, that is, the structure in which polysilicon (poly) and oxide (oxide) are stacked in sequence. With the continuous improvement of storage capacity requirements, the number of stacked layers of the OPOP structure is increasing. The formation of

Method used

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  • A 3D NAND memory device and its manufacturing method
  • A 3D NAND memory device and its manufacturing method
  • A 3D NAND memory device and its manufacturing method

Examples

Experimental program
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Embodiment 1

[0060] refer to figure 1 Shown is a schematic top view of a 3D NAND memory device chip according to an embodiment of the present invention. In this specific embodiment, the memory chip includes 4 plate storage areas, and in each plate (plate) storage area Contains multiple block storage areas. It can be understood that this is only an example, and there may be other design arrangements according to different designs, and the present invention is not limited thereto.

[0061] refer to figure 2 shown, for figure 1 A partially enlarged view of the middle region 40, which shows a ladder structure and a part of the first storage area. In the first storage area 10, a block is divided into three parts by grid line gaps, and each pair of grid line gaps There is a finger storage area in between, and the first storage area is an array area of ​​3D NAND storage units, which may contain one or more block storage areas.

[0062] In this embodiment, the grid line slits 46 of the ladder...

Embodiment 2

[0065] In this embodiment, parts different from those in Embodiment 1 will be described, and the same parts will not be repeated.

[0066] refer to image 3 shown, for figure 1 A partially enlarged view of the middle region 40, which shows a ladder structure and a part of the first storage area. In the first storage area 10, a block is divided into three parts by grid line gaps, and each pair of grid line gaps There is a finger storage area in between, and the first storage area is an array area of ​​3D NAND storage units, which may contain one or more block storage areas.

[0067] The sub-step region 41 is disposed between the gate line gaps of the corresponding block region of the step structure 40 , and the corresponding region of the step structure (not shown in the figure) on the other side is used for forming an interconnection structure. That is to say, the sub-step region 41 occupies the step structure region corresponding to a block region of the first storage regio...

Embodiment 3

[0069] In addition, a through contact hole area can also be provided in the direction of the bit line for connection with the CMOS circuit chip, refer to figure 1 and Figure 4 as shown, Figure 4 for figure 1 A partially enlarged view of the middle area 11, a via hole formation area 20 is arranged between the first storage area 10 and the second storage area 30, and the first storage area 10, the via hole formation area 20 and the second storage area 30 are along the bit line Arranged in order, the same as the first storage area 10, the second storage area, 20 includes the word line stack layer and the channel hole 12 in the word line stack layer; the via hole formation area 20 includes a via stack of oxide layer and nitride layer layer 24 , the through contact hole 26 penetrating through the via stack layer 24 and the insulating layer 22 on the sidewall of the via stack layer; the gate line gap 16 along the word line direction in the first storage area 10 and the second st...

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Abstract

The present invention provides a 3D NAND memory device, comprising: a base; a first storage area on the base, the first storage area includes a word line stack layer and a channel hole in the word line stack layer, side walls of the word line stack layer It is a ladder structure; there is a sub-ladder area in the ladder structure, the sub-ladder area is a stack of oxide layers and nitride layers, the sub-ladder area extends along the word line direction to the edge of the ladder structure, and the sub-ladder area is in contact with the ladder structure An insulating layer is provided on the side wall of the connection; a through contact hole is provided in the sub-step region; and a grid line gap in the ladder structure outside the sub-step region. The through contact hole of this structure is convenient to realize the connection between the storage device and the CMOS chip, and is easy to integrate with the existing process, especially when the thickness of the stack layer continues to increase, there is no need to etch the metal stack to form the through contact hole, which is beneficial to the process. Realization and continuous improvement of integration.

Description

technical field [0001] The invention relates to the field of flash memories, in particular to a 3D NAND memory device and a manufacturing method thereof. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the planar NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory is proposed. [0003] In the 3D NAND memory structure, the stacked 3D NAND memory structure is realized by stacking multiple layers of data storage units vertically. However, other circuits such as decoder, page buffer and latch ), etc., these peripheral circuits are all formed by CMOS devices, and the technology of CMOS devices cannot be integrated with 3D NAND devices. An array ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11519H01L27/11551H01L27/11565H01L27/11578H10B41/10H10B41/20H10B43/10H10B43/20
CPCH10B41/10H10B41/20H10B43/10H10B43/20
Inventor 吕震宇施文广吴关平万先进陈保友
Owner YANGTZE MEMORY TECH CO LTD