High voltage PMOS driving circuit

Abstract

The invention discloses a high voltage PMOS driving circuit, and relates to the technical field of driving circuits of field effect transistors. The driving circuit comprises a NAND gate, a pulse signal generation circuit, a level shift circuit, a trigger, a buffer circuit and a VS voltage generation circuit, wherein an enable signal input end EN and a signal input port INPUT are respectively connected with two input ports A and B of the NAND gate, an output port O of the NAND gate is connected with an input port IN of the pulse signal generation circuit, two output ports O _1 and O _2 of the level shift circuit are respectively connected with two input ports of the trigger, the output port of the trigger is connected with the input port IN of the buffer circuit, and the output port OUT of the buffer circuit is connected with a driving voltage output port HO. The driving circuit has the advantages of simple structure, easy realization, small power consumption, small switching loss, high conversion efficiency, wide working voltage range, and no need for a bootstrap circuit.

Description

technical field [0001] The invention relates to the technical field of drive circuits applied to field effect transistors, in particular to a high-voltage PMOS drive circuit. Background technique [0002] The drive circuit amplifies the power of the low-voltage logic control signal to drive the power tube to work reliably. Power tubes are generally divided into PMOS power tubes and NMOS power tubes. The ultimate goal of driving circuit design is to make power switching devices work in close to ideal switching states, reduce switching losses, and improve overall system efficiency and reliability. Traditional driver circuits are used to drive NMOS power transistors. Compared with NMOS power transistors, driving PMOS power transistors has smaller switching losses. Moreover, driving the PMOS power tube does not require a bootstrap circuit (boost circuit) structure, and the power tube can be turned on and off for a longer period of time or even kept in the on state. It is very...

AI Technical Summary

Problems solved by technology

However, since the source-gate voltage difference of high-voltage PMOS power transistors does not exceed 20V (the maximum does not exceed 30V), high-voltage PMOS power transistors can generally only be driven by discrete circuits, and power consumption, efficiency, and frequency are greatly affected. limit

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