Semiconductor structure and formation method thereof

[0031] The prior art method for forming a semiconductor structure has many problems, for example, it is difficult to control the height of the fin of the fin field effect transistor.

[0032] Now combining the semiconductor structure of the prior art, analyze the reasons why the height of the fin of the semiconductor structure is difficult to control:

[0033] Figure 1 to Figure 5 It is a schematic diagram of each step of a method for forming a semiconductor structure. The method for forming the semiconductor structure includes:

[0034] Please refer to figure 1 , A substrate 100 is provided, and a mask layer 110 is formed on the substrate 100.

[0035] Please refer to figure 2 Etch the substrate 100 using the mask layer 110 as a mask to form the initial fin 120.

[0036] Please refer to image 3 , Forming an isolation layer 131 covering the initial fin 120.

[0037] Please refer to Figure 4 , The isolation layer 131 is planarized by chemical mechanical polishing.

[0038] Please refer to Figure 5 , To the isolation layer 131 (such as Figure 4 Shown) is etched to expose the initial fin 120 (such as Figure 4 (Shown) part of the sidewall forms an isolation structure 130, and a part of the initial fin 120 exposed to the isolation structure 130 forms a fin 121.

[0039] Such as Figure 4 with Figure 5 As shown, in the method for forming the semiconductor structure, the isolation layer 131 is etched to expose a part of the sidewall of the initial fin 120 from the isolation layer 131 to form the fin 121. In the process of forming the fin 121, only the isolation layer 131 is etched, and the height of the fin 121 is controlled by controlling the etching rate and the etching time. However, during the etching process, the etching rate and the etching time are related to the distance between the fins 121 to be formed and the etching depth. Therefore, it is difficult to accurately control the height of the fin 121. The inaccuracy of the height of the fin 121 easily affects the width of the transistor channel, thereby affecting the impedance of the channel, and further affecting the electrical performance of the semiconductor structure.

[0040] In order to solve the technical problem, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first area and a second area; forming an etching stop layer on the substrate to form an etching The step of etching the barrier layer includes forming a first etching barrier layer on the surface of the substrate in the first region; forming a fin material layer on the substrate and the first etching barrier layer, the fin material layer and the first etching barrier layer The material of the etch stop layer is different; the fin material layer of the first region and the second region and the substrate of the second region are patterned, and a first opening exposing the etch stop layer is formed in the first region, and Forming an initial fin in the second region; forming an isolation layer covering the substrate between the first etching barrier layer at the first opening and the initial fin, and the etching barrier layer and the isolation layer have different constituent elements; The isolation layer is etched to generate etching by-products; in the step of etching the isolation layer, the etching by-products are detected, and the etching is performed until the etching by-products change.

[0041] Wherein, before the step of forming the fin material layer, an etching barrier layer is formed on the substrate, and the step of forming the etching barrier layer includes: forming a first etching barrier layer on the surface of the substrate in the first region, the isolation layer and The constituent elements of the etching barrier layer are different. In the subsequent step of etching the isolation layer, the thickness of the removed isolation layer can be controlled by detecting the composition of the generated etching byproducts, so as to control the height of the initial fin exposed by the isolation layer, so that the height of the fin is not excessive. Large or too small affects the impedance of the formed transistor channel, and thus the formed semiconductor structure has good electrical properties. When the etching byproduct changes, it indicates that the etching stop layer has been exposed. Stopping the etching to form the fins removes the isolation layer in the second area with the same thickness as the isolation layer in the first area, so that the height of the exposed initial fins is controlled by controlling the thickness of the removed isolation layer, and the initial fins exposed in the isolation layer The part constitutes the fin, thereby realizing the control of the height of the transistor fin.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0043] Figure 6 to Figure 12 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention.

[0044] Please refer to Image 6 , A substrate 200 is provided, and the substrate 200 includes a first region I and a second region II.

[0045] The substrate 200 is used to form a semiconductor structure.

[0046] In this embodiment, the first region I is used to form pseudo fins, and the height of the fins in the second region subsequently formed is controlled by detecting the height of the pseudo fins; the second region II is used to form a fin field Effect transistor.

[0047] In this embodiment, the material of the substrate 200 is monocrystalline silicon. In other embodiments, the substrate may also be a semiconductor substrate such as a germanium substrate, a silicon germanium substrate, or a silicon-on-semiconductor substrate.

[0048] Continue to refer Image 6 , An etch stop layer is formed, and the etch stop layer includes a first etch stop layer 210 on the surface of the first region I substrate 200.

[0049] The etch stop layer is used to control the height of the second region II fins formed subsequently.

[0050] It should be noted that in this embodiment, in order to simplify the process flow, the etch stop layer only includes the first etch stop layer 210. Therefore, the first etch stop layer 210 is the etch stop layer, and is used to control the height of the fins formed subsequently.

[0051] In this embodiment, the step of forming the first etching stop layer 210 includes: forming an initial first etching stop layer on the surface of the substrate 200 in the first region I and the second region II. The initial first etch barrier layer on the second region II is removed, and the initial first etch barrier layer on the first region I is retained to form the first etch barrier layer 210.

[0052] Specifically, in this embodiment, the initial first etch stop layer is formed on the surface of the substrate 200 in the first region I and the second region II by an epitaxial growth process.

[0053] In this embodiment, the process parameters of the epitaxial growth include: the reaction temperature is 600°C to 1100°C; the gas pressure is 1 torr to 500 torr; the reaction gases are silicon source gas, germanium source gas, chlorine gas, and hydrogen gas, and the silicon source gas is SiH 4 , SiH 2 Cl 2 Or Si 2 Cl 6 , The germanium source gas is GeH 4.

[0054] In this embodiment, the initial first etch stop layer on the second region II is removed by dry etching to form the first etch stop layer 210. In other embodiments, the initial first etch stop layer on the second region II can also be removed by wet etching.

[0055] In this embodiment, the material of the first etching stop layer 210 is a single crystal that can be lattice-matched with the fin material layer to be formed later, so as to provide a seed crystal for the fin material layer. Specifically, the material of the first etching stop layer 210 is single crystalline silicon germanium. The crystal lattice of silicon germanium has a good matching degree with that of the substrate 200. In other embodiments, the material of the first etching stop layer may also be a single crystal formed of germanium, silicon carbide or other group III to V elements, such as GaN and GaAs.

[0056] It should be noted that if the thickness of the first etch stop layer 210 is too small, it is easy to be etched and removed during subsequent etching of the substrate 200, and it is difficult to control the height of the fin; If the thickness of the etch stop layer 210 is too large, it is easy to increase the height difference between the surface of the fin material layer subsequently formed in the first region I and the second region II, thereby increasing the difficulty of controlling the height of the fin. Specifically, in this embodiment, the thickness of the first etching stop layer 210 is in the range of 10 nm to 1000 nm.

[0057] Please refer to Figure 7 A fin material layer 220 is formed on the surface of the substrate 200 and the etching stop layer 210, and the fin material layer 220 and the first etching stop layer 210 have different constituent elements.

[0058] The fin material layer 220 is used to form the fin of the fin-type field effect transistor.

[0059] In this embodiment, the step of forming the fin material layer 220 includes:

[0060] Forming an initial fin material layer on the first etch stop layer 210 in the first region I and the substrate 200 in the second region II;

[0061] The initial fin material layer is planarized by a chemical mechanical planarization process to form a fin material layer 220 so that the surfaces of the fin material layer 220 in the first region I and the second region II are flush.

[0062] The flattening treatment can make the surface of the fin material layer 220 flat, and can make the surface of the fin material layer 220 in the first region I and the second region II level, so as to better treat the subsequent second region II. The height of the fins is controlled.

[0063] In this embodiment, the material of the initial fin material layer is the same as the material of the substrate 200. The initial fin material layer of the same material as the substrate 200 has a good lattice matching with the substrate 200, and the formed fin material layer 220 has fewer defects and high quality. Specifically, the material of the initial fin material layer is monocrystalline silicon.

[0064] In this embodiment, the method for forming the initial fin material layer is an epitaxial growth process. The reaction gas of the epitaxial growth process includes silane.

[0065] In this embodiment, the material of the fin material layer 220 is the same as the material of the initial fin material layer, that is, the material of the fin material layer 220 is the same as the material of the substrate 200. Specifically, the material of the fin material layer 220 is also monocrystalline silicon.

[0066] It should be noted that the fin material layer 220 is used to form fins. If the thickness of the fin material layer 220 is too large or too small, it is easy to cause the fins to be too large or too small, thereby making the channel width too large. If it is too large or too small, it will affect the channel resistance and the electrical performance of the field effect transistor. Specifically, in this embodiment, the thickness of the fin material layer 220 in the first region I is 20 nm to 80 nm; the thickness of the fin material layer 220 in the second region II is 30 nm to 1080 nm.

[0067] Please refer to Figure 8 , Patterning the fin material layer 220 in the first region I and the second region II, forming a first opening 202 exposing the first etch stop layer 210 in the first region I, and in the second region II Forming a plurality of second openings 203;

[0068] The substrate 200 at the bottom of the second opening 203 is etched so that the depth of the second opening 203 is greater than the depth of the first opening 202 to form an initial fin 230 located between the adjacent second openings 203. The first opening 202 and the second opening 203 are used to subsequently accommodate the isolation layer; the initial fin 230 is used to form a fin.

[0069] It should be noted that in this embodiment, the etch stop layer only includes the first etch stop layer 210. Therefore, in this embodiment, the fin material layers in the first region I and the second region II are patterned 220 and the step of patterning the second region II substrate 200 are performed in the same patterning process.

[0070] In this embodiment, the first region I is used to form pseudo fins, and the height and line width of the fins in the subsequent second region II are controlled by detecting the pseudo fins. The line width refers to the fins. The width of the top end. Therefore, the step of patterning the fin material layer 220 of the first region I and the second region II includes: patterning the fin material layer 220 of the first region I to form the first region fin 231, the The first region fin 231 is a pseudo fin.

[0071] In this embodiment, the fin material layer 220 (such as Figure 7 The material shown) is the same as that of the substrate 200. Therefore, the step of patterning the fin material layer 220 in the first region I and the second region II and the substrate 200 in the second region II can be In the same patterning process.

[0072] Specifically, the step of patterning the fin material layer 220 of the first region I and the second region II and the substrate 200 of the second region II includes:

[0073] A mask layer 201 is formed on the fin material layer 220, and the mask layer 201 is used to define the size and position of the initial fin 230, and define the first etching stopper layer exposed in the subsequent first region I 210 size and position;

[0074] Using the mask layer 201 as a mask, the fin material layer 220 and the second region substrate 200 are etched to form the first region fin 231 in the first region I and in the second region The area II forms the initial fin 230.

[0075] In this embodiment, the mask layer 201 has a first pattern corresponding to the first region fin 231 and a second pattern corresponding to the initial fin 230, and the first pattern is the same as the second pattern. Therefore, in this embodiment, the top width of the first region fin 231 and the initial fin 230 are the same.

[0076] In this embodiment, the material of the mask layer 201 and the material of the fin material layer 220 are different. Specifically, the material of the mask layer 201 is silicon nitride or silicon oxynitride.

[0077] In this embodiment, the fin material layer 220 and the second region II substrate 200 are etched by a dry etching process. Dry etching is an anisotropic etching method, which has good profile control and line width control. Therefore, the line width of the initial fin 230 can be easily controlled. The etching adopts time control, and the etching has a higher selection ratio for the fin material layer 220 and the etching stop layer 210: the etching has a faster etching rate for the fin material layer 220, and the etching has a higher effect on the etching stop layer. The etching rate of 210 is slow or not etched. In the first region I, the etching basically stops when the etching stop layer 210 is exposed; while in the second region II, the etching will continue until the initial fin 230 has a predetermined height and the height of the initial fin 230 It is greater than the height of the fin 231 in the first region.

[0078] It should be noted that if the fin material layer 220 and the second region substrate 200 are etched, the etching selection ratio of the etching gas to the single crystal silicon and the first etching stop layer 210 is too small In the etching process, the first etching stop layer 210 is easily removed. Therefore, in this embodiment, the etching selection ratio of the etching gas to the fin material layer 220 and the first etching stop layer 210 is greater than 10; the etching gas to the substrate and the first etching stop layer 210 The etching selection ratio is greater than 10.

[0079] Subsequently, an isolation layer covering the substrate 200 between the first etching barrier layer at the bottom of the first opening 202 and the initial fin 230 is formed, and the isolation layer and the etching barrier layer have different constituent elements.

[0080] In this embodiment, the steps of forming an isolation layer covering the substrate 200 between the first etching stop layer 210 at the bottom of the first opening 202 and the initial fin 230 are as follows: Picture 9 with Picture 10 Shown.

[0081] Please refer to Picture 9 , Forming an initial isolation layer 241 whose surface is higher than the top surface of the initial fin 230.

[0082] In this embodiment, the material of the initial isolation layer 241 is silicon oxide. In other embodiments, the material of the initial isolation layer may also be silicon nitride or silicon oxynitride.

[0083] In this embodiment, the initial isolation layer 241 is formed by a chemical vapor deposition process. Chemical vapor deposition can form a uniform initial isolation layer 241 with few pinholes. In other embodiments, the initial isolation layer can also be formed by an atomic layer deposition process or a physical deposition process.

[0084] Please refer to Picture 10 , The initial isolation 241 shown by chemical mechanical polishing (such as Picture 9 As shown), a planarization process is performed to make the surfaces of the initial isolation layer in the first region I and the second region II level to form an isolation layer 242.

[0085] In this embodiment, the planarization process makes the surface of the initial isolation layer 241 in the first region I and the second region II level, which can reduce the difficulty of controlling the height of the fin. In addition, the flattening treatment can increase the flatness of the surface of the isolation layer 242 and increase the control accuracy.

[0086] In this embodiment, the material of the isolation layer 242 is the same as the material of the initial isolation layer 241. Specifically, the material of the isolation layer 242 is silicon oxide.

[0087] Please refer to Picture 11 , To the isolation layer 242 (such as Picture 10 As shown), etching is performed until the etching stop layer is exposed to form an isolation structure 240.

[0088] In the step of etching the isolation layer 242, etching by-products are generated. The etching by-products are detected, and the isolation layer 242 is etched until the etching by-products change to form an isolation structure 240. The isolation structure 240 exposes the initial fin 230 (such as Picture 10 Shown) part of the side wall. The part of the initial fin 230 exposed from the isolation structure 240 constitutes the fin 232.

[0089] In this embodiment, the etching gas is CF 4 , HF and CF 2 , And the constituent elements of the etching gas do not include germanium.

[0090] It should be noted that, in this embodiment, the material of the first etching stop layer 210 is silicon germanium, and the material of the isolation layer 242 is silicon oxide. In the step of detecting the etching by-products, if germanium is detected in the etching by-products, the surface of the etching stop layer 210 has been exposed, and the etching is stopped. The height of the formed fin 232 is equal to the height of the fin 231 in the first region above the etching stop layer 210, that is, the height of the fin 232 is the same as the height of the fin material layer 220 (such as Figure 7 (Shown) have the same thickness. Specifically, the height of the fin 232 is 20 nm to 80 nm.

[0091] It should be noted that after the step of etching the isolation layer 242, the forming method further includes:

[0092] Such as Picture 12 As shown, a gate structure spanning the fin 232 is formed, and the gate structure is located on part of the sidewall surface and the top surface of the fin 232.

[0093] In this embodiment, the gate structure also straddles the first area fin 231 and covers part of the sidewall and top surface of the first area fin 231.

[0094] In this embodiment, the gate structure includes: a gate dielectric layer 251 spanning the fin 232 and a gate layer 252 located on the surface of the gate dielectric layer 251. The gate dielectric layer 251 is used to achieve electrical insulation between the gate layer 252 and the fin 232; the gate layer 252 is used to form the gate of the transistor, and the fin 232 is formed under the gate layer 252 Transistor channel.

[0095] In this embodiment, the material of the gate dielectric layer 251 is a high-k dielectric material. Specifically, the material of the gate dielectric layer 251 is titanium nitride or tantalum nitride.

[0096] In this embodiment, the material of the gate layer 252 is titanium aluminum alloy. In other embodiments, the material of the gate layer 252 may also be tungsten.

[0097] A source region and a drain region are formed in the fins 232 on both sides of the gate structure, which will not be repeated here.

[0098] Figure 13 to Figure 18 It is a schematic diagram of each step structure of another embodiment of the method for forming a semiconductor structure of the present invention.

[0099] The similarities between this embodiment and the previous embodiment will not be repeated here. The differences include: the first etching stop layer and the fin material layer have different constituent elements; the etching stop layer also includes The second etch stop layer on the surface of the first etch stop layer at the bottom of the first opening, the material of the second etch stop layer is different from the constituent elements of the fin material layer;

[0100] The step of forming an etching stop layer further includes: after the step of patterning the fin material layer in the first region and the second region, forming a second etching stop layer, the second etching stop layer being located in the first area The surface of the first etching barrier layer at the bottom of the opening and the bottom surface of the second opening;

[0101] Before etching the substrate at the bottom of the second opening, the forming method further includes: etching and removing the second etching stopper layer on the bottom surface of the second opening, and leaving the first etching covering the bottom of the first opening The second etch stop layer on the surface of the stop layer.

[0102] After the step of etching the isolation layer, the forming method further includes removing the second etching stop layer.

[0103] Specifically, please refer to Figure 13 , Patterning the fin material layers of the first area A and the second area B to form a first opening 302 exposing the first etching stop layer 310, and forming a plurality of second areas in the second area B The opening 303, and the precursor fin 333 located between the second openings 303.

[0104] In this embodiment, the second region B is used to form dummy fins. Therefore, in the step of patterning the fin material layer of the first region A, a plurality of first openings 302 and located between the second openings 302 are formed. Between the first area fins 331.

[0105] In this embodiment, the first etch stop layer 310 is used as an etch stop layer for etching the fin material layer. The constituent elements of the first etching stop layer 310 and the substrate 300 are different.

[0106] In this embodiment, the step of patterning the fin material layer includes: using the mask layer 301 as a mask, etching the fin material layer until the etching stop layer is exposed, resulting in a An etching by-product.

[0107] In this embodiment, the first etch stop layer 310 can be used as an etch stop layer for etching the fin material layer.

[0108] Specifically, in this embodiment, the material of the first etch stop layer 310 is silicon germanium. In the step of patterning the fin material layer, the first etching byproduct is detected, and the etching is stopped when germanium appears in the first etching byproduct, so as to control the subsequent second etching stop layer s position.

[0109] It should be noted that in this embodiment, the etch stop layer further includes a second etch stop layer that covers the first etch stop layer 310 at the bottom of the first opening 302. The following combination Figure 14 Be explained.

[0110] Please refer to Figure 14 After the step of forming the first opening 302, a second etch stop layer 311 covering the first etch stop layer 310 at the bottom of the first opening 302 is formed.

[0111] The second etching stop layer 311 and the fin material layer have different constituent elements.

[0112] In this embodiment, the second etching stop layer 311 is used to define the height of the fin to be formed later.

[0113] In this embodiment, the material of the second etching stop layer 311 is different from the material of the substrate 300. The second etch stop layer 311 having a different material from the substrate 300 is not easily etched in the subsequent step of etching the substrate 300 in the second region B, so that the control accuracy of the height of the fin can be increased.

[0114] In this embodiment, the material of the second etching stop layer 311 is silicon nitride. In other embodiments, the second etch stop layer may also be silicon oxynitride.

[0115] It should be noted that if the thickness of the second etching stop layer 311 is too small, it is difficult to control the height of the fins formed later; if the thickness of the second etching stop layer 311 is too large, it is easy to The removal process brings difficulties. Specifically, in this embodiment, the thickness of the second etching stop layer 311 is 5 nm-20 nm.

[0116] In this embodiment, the second etch stop layer 311 is formed in the first area A and the second area B by a chemical vapor deposition process. The chemical vapor deposition process is simple and the process difficulty is low. In other embodiments, the second etch stop layer may also be formed by a physical vapor deposition process or an atomic layer deposition process.

[0117] Please refer to Figure 15 Etch the substrate 300 at the bottom of the second opening 303 so that the depth of the second opening 303 is greater than that of the first opening 302 (such as Figure 14 As shown), the initial fin 330 is formed between the adjacent second openings 303.

[0118] It should be noted that, in this embodiment, the second region B precursor fin 333 (such as Figure 14 A second etching stop layer 311 is formed between the above). Therefore, before the step of patterning the second region B substrate 300, it further includes: forming a first region fin 331 covering the first region A and a photoresist 30 filling the first opening 302; The photoresist 30 is a mask, and the second etching stop layer 311 is etched to remove the second etching stop layer 311 between the initial fins 330 in the second region B.

[0119] Specifically, in this embodiment, the second etching stop layer 311 is removed by dry etching. The dry etching is anisotropic, and the second etching stop layer 311 covering part of the sidewall of the initial fin 330 can be retained, so that the initial fin 330 can be protected.

[0120] It should also be noted that in the step of patterning the substrate 300 of the second region B, the photoresist 30 covers the second etching stop layer 311 and the first etching stop layer 310 of the first region A, The second etch stop layer 311 and the first etch stop layer 310 can be protected during the etching of the substrate 300. Therefore, the etching damage to the second etch stop layer 311 and the first etch stop layer 310 is small, the requirement on the etching process is low, and the etching difficulty is small.

[0121] Please refer to Figure 16 , The isolation layer 341 is filled between the first area fin 331 of the first area A and the initial fin 330 of the second area B. This step is the same as the previous embodiment, and will not be repeated here.

[0122] Please refer to Figure 17 , To the isolation layer 341 (such as Figure 16 (Shown) etching is performed until the etching stop layer is exposed.

[0123] In the step of etching the isolation layer, an etching by-product is generated, and the etching by-product is detected, and the isolation layer is etched until the etching by-product changes, forming an isolation structure 340, The isolation structure 340 exposes the initial fin 330 (such as Figure 16 Shown) part of the side wall. The part of the initial fin 330 exposed from the isolation structure 340 constitutes the fin 332.

[0124] It should be noted that in this embodiment, the etching gas is CF 4 , HF and CF 2 , And the constituent elements of the etching gas do not include nitrogen.

[0125] In this embodiment, the material of the isolation layer 341 is silicon oxide, and the material of the second etching stop layer 311 is silicon nitride. In the step of etching the isolation layer 341, the etching byproduct does not contain nitrogen, and when the isolation layer 341 is exposed, the etching byproduct contains nitrogen. Therefore, the etching stops when the second barrier layer 311 is exposed.

[0126] In this embodiment, the second etch stop layer 311 is used as an etch stop layer for etching the isolation layer 341, that is, the etching stops when the second etch stop layer 311 is exposed. The second etching stop layer 311 is etched without direct contact with the etching gas. Therefore, the surface of the second etching stop layer 311 is relatively flat, and the height of the fin 332 can be controlled more accurately. In other embodiments, in the step of etching the isolation layer, when the first barrier layer is exposed, that is, when germanium is contained in the etching by-product, the etching may be stopped.

[0127] Specifically, in this embodiment, the material of the second etching stop layer 311 is silicon nitride, and the material of the isolation layer is silicon oxide. In the step of detecting the etching by-products, if nitrogen is detected in the etching by-products, the surface of the second etching stop layer 311 has been exposed, and the etching is stopped. The height of the formed fin 332 is equal to the thickness of the fin material layer above the second etching stop layer 311, that is, the height of the fin 332 can be adjusted by adjusting the thickness of the fin material layer 320.

[0128] Please refer to Figure 18 , Remove the second etching stop layer 311 (such as Figure 17 Shown).

[0129] In this implementation, the second etching stop layer 311 is removed by dry etching. In other embodiments, the second etching stop layer may also be removed by wet etching.

[0130] In summary, in the method for forming a semiconductor structure of the present invention, before the step of forming the fin material layer, an etching stop layer is formed on the substrate, and the step of forming the etching stop layer includes: forming a first region on the surface of the substrate An etching stop layer, the isolation layer and the etching stop layer have different constituent elements. In the subsequent step of etching the isolation layer, the thickness of the removed isolation layer can be controlled by detecting the composition of the generated etching byproducts, so as to control the height of the initial fin exposed by the isolation layer, so that the height of the fin is not excessive. Large or too small affects the impedance of the formed transistor channel, and thus the formed semiconductor structure has good electrical properties. When the etching byproduct changes, it indicates that the etching stop layer has been exposed. Stopping the etching to form the fins removes the isolation layer in the second area with the same thickness as the isolation layer in the first area, so that the height of the exposed initial fins is controlled by controlling the thickness of the removed isolation layer, and the initial fins exposed in the isolation layer The part constitutes the fin, thereby realizing the control of the height of the transistor fin.

[0131] Further, the second etch stop layer can be used as an etch stop layer to etch the isolation layer, to compensate for defects caused by the first etch stop layer being etched when the fin material layer is etched, and to increase the etching stop The flatness of the surface of the layer, thereby increasing the accuracy of the height control of the fin. In addition, the second etch stop layer can also protect the first etch stop layer during the step of etching the fin material layer, and reduce the influence on the first etch stop, thereby reducing the etching process. Difficulty.

[0132] Correspondingly, the present invention also provides a semiconductor structure including: a substrate including a first region and a second region; a first etching stopper layer located on the substrate in the first region; The fin material layer on the etch stop layer has a first opening in the fin material layer, and the first opening exposes the first etch stop layer; the initial fin on the substrate in the second region, so The material of the first etch stop layer is different from that of the initial fin; an isolation structure covering part of the sidewall of the initial fin in the second region, the isolation structure exposing part of the sidewall of the initial fin, and exposed to the initial fin of the isolation structure Part constitutes a fin part; a gate structure covering the fin part.

[0133] Specifically, please refer to Picture 12 , The semiconductor structure includes:

[0134] The substrate 200 includes a first area I and a second area I. The substrate 200 is used to form a semiconductor structure.

[0135] In this embodiment, the first region I substrate 200 is used to form dummy fins, and the second region II substrate 200 is used to form field effect transistors.

[0136] In this embodiment, the material of the substrate 200 is monocrystalline silicon. In other embodiments, the substrate may also be a semiconductor substrate such as a germanium substrate, a silicon germanium substrate, or a silicon-on-semiconductor substrate.

[0137] The first etch stop layer 210 is located on the substrate 200 in the first region I. The first etching stop layer 210 is used to control the height of the fin. The material of the first etch stop layer 210 is different from the material of the substrate 200 and the fins.

[0138] The first etching stop layer 210 is a single crystal that can achieve lattice matching with the substrate 200. Therefore, the substrate 200 can provide a seed crystal for the first etch stop layer 210.

[0139] In addition, the first etch stop layer 210 and the first region fin 231 can achieve a lattice-matched single crystal. Specifically, in this embodiment, the material of the first etching stop layer 210 is single-crystalline silicon germanium. The crystal lattice of silicon germanium has a good matching degree with that of the substrate 200. In other embodiments, the material of the first etching stop layer may also be a single crystal formed of germanium, silicon carbide or other group III to V elements.

[0140] It should be noted that if the thickness of the first etching stop layer 210 is too small, it is easy to be etched and removed during the process of forming the semiconductor structure, and it is difficult to control the height of the fin; If the thickness of 210 is too large, it is easy to reduce the integration degree of the semiconductor structure. Specifically, in this embodiment, the thickness of the first etching stop layer 210 is in the range of 10 nm to 1000 nm.

[0141] The fin material layer located on the substrate 200 in the first region I has a first opening in the fin material layer, and the first opening exposes the surface of the first etching stop layer 210. The fin material layer is used to control the height of the fin. The first opening is used to accommodate the gate structure

[0142] In this embodiment, the fin material layer is a first region fin 231 formed on the etching stop layer 210. The first area fin 231 is used to form a pseudo fin.

[0143] In this embodiment, the material, height, and line width of the fins 231 in the first region are the same as those of the subsequent fins. Specifically, the material of the first area fin 231 is monocrystalline silicon; the height of the first area fin 231 is 20 nm to 80 nm; the top width of the first area fin 231 is 5 nm to 15 nm.

[0144] In this embodiment, the depth of the first opening is related to the height of the subsequent fin. If the depth of the first opening is too large or too small, it is easy to cause the height of the fin to be too large or too small. In this embodiment, the depth of the first opening is the same as the height of the fin. Specifically, the depth of the first opening is 20 nm to 80 nm.

[0145] The initial fin located on the substrate 200 in the second region II, and the first etch stop layer 210 is different from the substrate 200 and the initial fin. The initial fin is used to form a fin.

[0146] In this embodiment, the initial fin is a single-layer structure formed of monocrystalline silicon. The initial fin of the single-layer structure has a high degree of lattice matching and few lattice defects. Specifically, the material of the initial fin is monocrystalline silicon. In other embodiments, the initial fin may also be a laminated structure formed by two single crystals.

[0147] In this embodiment, if the width of the initial fin is too large or too small, the channel resistance of the transistor will be too large or too small, which will easily affect the electrical performance of the transistor. Specifically, in this embodiment, the width of the initial fin is in the range of 5 nm to 15 nm.

[0148] The isolation structure 240 covering the sidewall of the initial fin portion of the second region II exposes the sidewall of the initial fin portion.

[0149] The isolation structure 240 is used to achieve electrical insulation between the initial fins. The initial fin exposed in the isolation structure 240 forms a fin 232, and the fin 232 is used to form a transistor channel.

[0150] In this embodiment, the material of the initial isolation structure 240 is silicon oxide. In other embodiments, the material of the initial isolation structure 240 may also be silicon nitride or silicon oxynitride.

[0151] In this embodiment, if the height of the fin portion 232 is too small, it is easy to cause the channel cross section to be too small, thereby causing the channel resistance to be too large; the height of the fin portion 232 is too large, which easily reduces the integration degree of the semiconductor structure. Specifically, in this embodiment, the height of the fin 232 (that is, the distance from the top surface of the initial fin to the surface of the isolation structure) is in the range of 20 nm to 80 nm.

[0152] In this embodiment, if the width of the fin portion 232 is too small, it is easy to cause the channel cross section to be too small, thereby causing the channel resistance to be too large; the width of the fin portion 232 is too large, which easily reduces the integration degree of the semiconductor structure. Specifically, in this embodiment, the width of the fin 232 is in the range of 5 nm to 15 nm.

[0153] It should be noted that the semiconductor structure of the present invention further includes: a gate structure spanning the fin 232. The gate structure is located on part of the sidewall and top surface of the fin 232. The fin 232 under the gate structure constitutes a transistor channel; the source region and the drain region in the fin 232 on both sides of the gate structure.

[0154] In this embodiment, the gate structure also straddles the first area fin 231 and covers part of the sidewall and top surface of the first area fin 231.

[0155] In this embodiment, the gate structure includes: a gate dielectric layer 251 spanning the fin portion 232 and the first region fin portion 231 and a gate layer 252 located on the surface of the gate dielectric layer 251. The gate dielectric layer 251 is used to achieve electrical insulation between the gate layer 252 and the fin 232; the gate layer 252 is used to form the gate of the transistor.

[0156] In this embodiment, the material of the gate dielectric layer is a high-k dielectric material. Specifically, the material of the gate dielectric layer 251 is titanium nitride or tantalum nitride.

[0157] In this embodiment, the material of the gate layer 252 is titanium aluminum alloy. In other embodiments, the material of the gate layer 252 is tungsten.

[0158] In summary, in the semiconductor structure of the present invention, a first etch stop layer is formed on the surface of the substrate in the first region, and the first etch stop layer can be used to define the height of the fin. In the subsequent step of etching the isolation layer, the thickness of the removed isolation layer can be controlled by detecting the composition of the generated etching byproducts, so as to control the height of the initial fin exposed by the isolation layer.

[0159] Although the present invention is disclosed as above, the present invention is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.