Semiconductor structure and formation method thereof

A semiconductor and isolation structure technology, applied in the field of semiconductor structure and its formation, can solve the problem of difficult control of the fin height of transistors, achieve good electrical performance, reduce difficulty, and reduce the effect of impact

Active Publication Date: 2017-08-11
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the method for forming the semiconductor structure in the prior art has the disadvantage that it is

Method used

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  • Semiconductor structure and formation method thereof
  • Semiconductor structure and formation method thereof
  • Semiconductor structure and formation method thereof

Examples

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[0031] The prior art method for forming a semiconductor structure has many problems, for example, it is difficult to control the height of the fin of the fin field effect transistor.

[0032] Now combining the semiconductor structure of the prior art, analyze the reasons why the height of the fin of the semiconductor structure is difficult to control:

[0033] Figure 1 to Figure 5 It is a schematic diagram of each step of a method for forming a semiconductor structure. The method for forming the semiconductor structure includes:

[0034] Please refer to figure 1 , A substrate 100 is provided, and a mask layer 110 is formed on the substrate 100.

[0035] Please refer to figure 2 Etch the substrate 100 using the mask layer 110 as a mask to form the initial fin 120.

[0036] Please refer to image 3 , Forming an isolation layer 131 covering the initial fin 120.

[0037] Please refer to Figure 4 , The isolation layer 131 is planarized by chemical mechanical polishing.

[0038] Please refe...

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Abstract

The invention provides a semiconductor structure and a formation method thereof. The formation method comprises the steps that a substrate is provided, and the substrate comprises a first region and a second region; an etching barrier layer is formed on the substrate, and the steps of forming the etching barrier layer comprise that a first etching barrier layer is formed on the surface of the substrate of the first region; a fin material layer is formed on the substrate and the first etching barrier layer, and the fin material layer and the first etching barrier layer are different in material; the fin material layer of the first region and the second region and the substrate of the second region are patterned, a first opening from which the etching barrier layer is exposed is formed in the first region, and initial fins are formed in the second region; an isolating layer covering the first etching barrier layer of the first opening and the substrate between the initial fins is formed, and the etching barrier layer and the isolating layer are different in component elements; and the isolating layer is etched to generate etching by-product, the etching by-product is detected and etching is performed until the etching by-product changes. Control of the transistor fin height can be realized through the etching barrier layer.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration, and the effective length of the gate is also continuously reduced, resulting in weakening of the control ability of the gate to the channel. [0003] The gate of the Fin Field-Effect Transistor (FinFET) has a forked 3D structure similar to a fish fin. The channel of the FinFET protrudes from the surface of the substrate to form a fin, and the gate covers the top surface and sidewall of the fin, so that an inversion layer is formed on each side of the channel, which can control the connection and connection of the circuit on both sides of the circuit. disconnect. This design can increase the control of the gate to...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L29/78
CPCH01L29/66795H01L29/6681H01L29/785
Inventor 刘继全龚春蕾
Owner SEMICON MFG INT (SHANGHAI) CORP
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