3D NAND storage device and manufacturing method thereof

A technology of storage devices and storage areas, applied in the field of flash memory, can solve the problems of increasing, the process cannot be integrated with 3D NAND devices, etc., and achieve the effect of easy process integration

Active Publication Date: 2017-08-18
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In the 3D NAND memory structure, the stacked 3D NAND memory structure is realized by stacking multiple layers of data storage units vertically. However, other circuits such as decoder, page buffer and latch ), etc., these peripheral circuits are all formed by CMOS devices, and the technology of CMOS devices cannot be integrated with 3D NAND devices. An arr

Method used

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  • 3D NAND storage device and manufacturing method thereof
  • 3D NAND storage device and manufacturing method thereof
  • 3D NAND storage device and manufacturing method thereof

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0056] In the embodiment of the present invention, the via hole forming region 20 is arranged between two storage regions in the direction of the bit line, and the first storage region 10 and the second storage region 30 are regions for forming an array of memory cells. The design can be one or more block storage areas.

[0057] refer to figure 1 Shown is a schematic top view of a 3D NAND memory device chip according to an embodiment of the present invention. In this specific embodiment, the memory chip includes 4 plate storage areas, and in each plate (plate) storage area It includes a plurality of block storage areas, and the via hole forming area 20 is formed in the middle part of a slice storage area, and passes through the entire slice storage area along the word line direction. It can be understood that this is only an example, and there may be other design arrangements according to different designs, and the present invention is not limited thereto.

[0058] refer to ...

Embodiment 2

[0077] In this example, refer to image 3 As shown, the block storage areas are separated by gate line gaps 170, the direction of the gate line gaps 170 is the word line direction, the gate line gaps are parallel to each other, and the finger storage area is between a pair of gate line gaps 170. exist image 3 In the specific embodiment shown, a gate line gap divides a block storage area into three finger storage areas, which can be divided into two or more finger storage areas according to different design requirements.

[0078] As described above, refer to Figure 5As shown, the gate line gap 170 penetrates to the bottom of the stacked layer, the sidewall of the gate line gap 170 is an oxide layer, the filling material is metal, such as W, and a doped region is formed under it, which is set in the middle of the finger storage region There is a top select gate cut (Top Select Gate Cut) 180, which divides the top select gate of the storage area into two parts, and the top se...

Embodiment 3

[0085] In this embodiment, the parts different from those in the second embodiment will be described, and the same parts will not be repeated.

[0086] refer to Figure 4 As shown, a pair of gate line gaps 172 parallel to each other extending to the insulating ring 160 are formed in the block stack layers of the first region 110 and the third region 130, and the insulating ring 160 along the direction perpendicular to the gate line gaps The boundary of the slit extends at least to a region outside the pair of mutually parallel gate line gaps 170, so that the insulating ring 160 stacks the blocks of the first region 110 and the third region 130 between the pair of mutually parallel gate line gaps 172 The metal layer in the block stack is completely blocked, that is, the top select gates in the memory region on both sides of the insulating ring 160 cannot be connected through the top metal layer in the block stack layer.

[0087] In this embodiment, the outer side of the first ...

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Abstract

The invention provides a 3D NAND storage device and a manufacturing method thereof. The storage device comprises a substrate, a first storage region, a through hole formation region and a second storage region which are sequentially arranged along a bit line direction of the substrate, and a grid gap, wherein the first and second storage regions comprise storage stacking layers and channel holes in the storage stacking layers, the through hole formation region is formed between the first storage region and the second storage region, the through hole formation region comprises a through hole stacking layer in which an oxide layer and a nitride layer are stacked at an interval, a penetrating contact hole penetrating through the through hole stacking layer and an insulation layer on a side wall of the through hole stacking layer, and the grid gap is arranged between the first storage region and the second storage region. The storage device is advantaged in that connection with a CMOS chip can be realized through the penetrating contact hole, integration with the process in the prior art is easy, especially when thickness of the stacking layer continuously increases, the penetrating contact hole can be formed without metal stacking etching, and process realization and continuous integration level improvement are facilitated.

Description

technical field [0001] The invention relates to the field of flash memories, in particular to a 3D NAND memory device and a manufacturing method thereof. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the planar NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory is proposed. [0003] In the 3D NAND memory structure, the stacked 3D NAND memory structure is realized by stacking multiple layers of data storage units vertically. However, other circuits such as decoder, page buffer and latch ), etc., these peripheral circuits are all formed by CMOS devices, and the technology of CMOS devices cannot be integrated with 3D NAND devices. An array ...

Claims

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Application Information

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IPC IPC(8): H01L27/11582H01L27/11556
CPCH10B41/27H10B43/27
Inventor 吕震宇施文广吴关平万先进陈保友
Owner YANGTZE MEMORY TECH CO LTD
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