3D NAND storage device and manufacturing method thereof

Abstract

The invention provides a 3D NAND storage device and a manufacturing method thereof. The storage device comprises a substrate, a first storage region, a through hole formation region and a second storage region which are sequentially arranged along a bit line direction of the substrate, and a grid gap, wherein the first and second storage regions comprise storage stacking layers and channel holes in the storage stacking layers, the through hole formation region is formed between the first storage region and the second storage region, the through hole formation region comprises a through hole stacking layer in which an oxide layer and a nitride layer are stacked at an interval, a penetrating contact hole penetrating through the through hole stacking layer and an insulation layer on a side wall of the through hole stacking layer, and the grid gap is arranged between the first storage region and the second storage region. The storage device is advantaged in that connection with a CMOS chip can be realized through the penetrating contact hole, integration with the process in the prior art is easy, especially when thickness of the stacking layer continuously increases, the penetrating contact hole can be formed without metal stacking etching, and process realization and continuous integration level improvement are facilitated.

Description

technical field [0001] The invention relates to the field of flash memories, in particular to a 3D NAND memory device and a manufacturing method thereof. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the planar NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory is proposed. [0003] In the 3D NAND memory structure, the stacked 3D NAND memory structure is realized by stacking multiple layers of data storage units vertically. However, other circuits such as decoder, page buffer and latch ), etc., these peripheral circuits are all formed by CMOS devices, and the technology of CMOS devices cannot be integrated with 3D NAND devices. An array ...

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Problems solved by technology

[0003] In the 3D NAND memory structure, the stacked 3D NAND memory structure is realized by stacking multiple layers of data storage units vertically. However, other circuits such as decoder, page buffer and latch ), etc., these peripheral circuits are all formed by CMOS devices, and the technology of CMOS devices cannot be integrated with 3D NAND devices. An array of vias electrically connects the two together

The stacking in the 3D NAND memory array mainly adopts the OPOP structure, that is, the structure in which polysilicon (poly) and oxide (oxide) are stacked in sequence. With the continuous improvement of storage capacity requirements, the number of stacked layers of the OPOP structure is increasing. The formation of

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