ESD protection circuit structure of silicon-gate MOS integrated circuit

Abstract

The invention discloses an ESD protection circuit structure of a silicon-gate MOS integrated circuit. The ESD protection circuit structure comprises an NMOS (N-channel metal oxide semiconductor) transistor, an internal circuit, a port and an N-type active region injection resistor, and is characterized in that the NMOS transistor is connected with the internal circuit and the port, the NMOS transistor is provided with the N-type active region injection resistor, the N-type active region injection resistor is connected with the internal circuit and the port, and the internal circuit is connected with the port. The NMOS transistor is provided with the N-type active region injection resistor, thereby not only reducing the area of the integrated circuit layout, but also ensuring that most static electricity is firstly discharged through the NMOS transistor and then connected to the internal circuit through the N-type active region injection resistor, being good in electrostatic discharge effect, facilitating circuit protection and being low in cost.

Description

technical field [0001] The invention relates to the technical field of integrated circuit structures, in particular to a silicon gate MOS integrated circuit ESD protection circuit structure. Background technique [0002] The ESD protection of traditional silicon-gate MOS integrated circuits has many circuits with simple structures, among which the gate is directly grounded or the gate is grounded through a resistor. It is difficult for this circuit to ensure that the port first passes through the NMOS tube (which works The main reason is that the parasitic NPN triode) discharges static electricity, and then discharges static electricity through the resistor, which is easy to burn the resistor, or the resistance is relatively high, and the static voltage and energy reaching the chip are relatively high, and the single-stage protection effect is not good. The disadvantage of the level protection area is too large. The above deficiencies are worth addressing. Contents of the...

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Problems solved by technology

[0002] The ESD protection of traditional silicon-gate MOS integrated circuits has many circuits with simple structures, among which the gate is directly grounded or the gate is grounded through a resistor. It is difficult for this circuit to ensure that the port first passes through the NMOS tube (which works The main reason is that the parasitic NPN triode) discharges static electricity, and then discharges static electricity through the resistor, which is easy to burn the resistor, or the resistance is relatively high, and the static voltage and energy reaching the chip are relatively high, and the single-stage protection effect is not good. Disadvantages of large level protection area

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