A low-cost high-speed true random number generator
A true random number generator technology, applied in the field of low-cost high-speed true random number generators, to achieve the effect of improving random number characteristics and reducing hardware resource overhead
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Embodiment 1
[0030] Embodiment 1: as figure 1 Shown is the overall hardware structure diagram of Embodiment 1 of the present invention, which includes 3 multiplexing units and two branches formed by series connection of 2 NOT gates, and two adjacent multiplexing units are connected by a NOT gate door connection. Therefore, there are 9 NOT gates and 3 XOR gates in the chain oscillator circuit, and these 9 NOT gates and 3 XOR gates form 4 oscillation rings in total.
[0031] The head oscillation ring consists of three NOT gates and one XOR gate, namely figure 1 The leftmost oscillation ring in the virtual frame of the medium-chain oscillator, in the first oscillation ring, three NOT gates are connected in series in sequence, and the output terminal of the third NOT gate is connected with the input terminal of the first NOT gate to form a loop. An XOR gate is inserted between the second NOT gate and the third NOT gate, the XOR gate and the third NOT gate form a multiplexing unit, and the XO...
Embodiment 2
[0037] Embodiment 2: as figure 2 Shown is the overall hardware structure diagram of Embodiment 2 of the present invention, which includes 4 multiplexing units and two branches formed by series connection of 2 NOT gates, and two adjacent multiplexing units are connected by a NOT gate door connection. Therefore, there are 11 NOT gates and 4 XOR gates in the chain oscillator circuit, and these 11 NOT gates and 4 XOR gates form 5 oscillation rings in total. Both the head oscillation ring and the tail oscillation ring are composed of three NOT gates and an exclusive OR gate, and the three oscillation rings between the head oscillation ring and the tail oscillation ring are the middle oscillation rings.
[0038] The flip-flop array module is composed of 15 D flip-flops, and the output signals of these 15 D flip-flops are all input into the XOR gate array as the input signal of the XOR gate array. The XOR gate array is composed of 14 XOR gates, and the output signal of the XOR gat...
Embodiment 3
[0040] Embodiment 3: as image 3 Shown is the overall hardware structure diagram of Embodiment 3 of the present invention, which includes 5 multiplexing units and two branches formed by series connection of 2 NOT gates, and two adjacent multiplexing units are connected by a NOT gate door connection. Therefore, there are 13 NOT gates and 5 XOR gates in the chain oscillator circuit, and these 13 NOT gates and 5 XOR gates form 6 oscillation rings in total. Wherein, both the head oscillation ring and the tail oscillation ring are composed of three NOT gates and an exclusive OR gate, and the four oscillation rings between the head oscillation ring and the tail oscillation ring are middle oscillation rings.
[0041] The flip-flop array module is composed of 18 D flip-flops, and the output signals of these 18 D flip-flops are all input into the XOR gate array as the input signal of the XOR gate array. The XOR gate array is composed of 17 XOR gates, and the output signal of the XOR ...
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