Manufacture method for flip-chip and bare chip assembly

Abstract

The invention relates to the semiconductor field and discloses a manufacture method for a flip-chip and a bare chip assembly. The manufacture method comprises steps of performing metallization layer etching on a preset position of a bare chip on which metal spurting technology is finished, wherein the preset position is an area beyond a position of a copper column to be electroplated on the bare chip, covering a film protection layer in the preset position of the bare chip and hardening the film protection layer, and electroplating the copper column in the position of the copper column to be electroplated. Through the arrangement, the manufacture method and the bare chip assembly add an extra protection layer on the bare chip in the prior art, which effectively alleviates a potential damage on the copper column which is caused by a tangential stress around the copper column, enhances protection on the flip-chip copper column protection and improves packaging yield rate and reliability.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to chip packaging technology. Background technique [0002] The Flip chip packaging process is a hot spot in the field of semiconductor packaging today. Compared with the traditional wire-bonding packaging process, the Flip chip packaging process faces the active area of ​​the bare chip to the substrate. Solder bumps (solder balls and copper pillars) arranged in an array on the chip realize the interconnection between the bare chip and the substrate. The bare chip is directly mounted on the substrate in an inverted manner, which greatly shortens the interconnection length, and has small RC delay and heat dissipation. Good performance, high IO density, small package area, and thin thickness are very suitable for the current development direction of IC products with high speed, high performance, high IO density, and miniaturization. However, in the current mainstream Flip chip packaging...

AI Technical Summary

Problems solved by technology

[0005] It is not difficult to see that in the prior art, the PI layer covered on the surface of the chip mainly exists as a stress buffer layer for the copper pillars, and as the diameter of the copper pillars gradually shrinks, the influence of the tangential stress on the strength of the copper pillars becomes increasingly prominent. This brings about related issues such as packaging yield and reliability.

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