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Design method suitable for near-threshold and sub-threshold low electric leakage standard cell

A technology of standard unit and design method, applied in CAD circuit design, calculation, electrical and digital data processing, etc., can solve the problems of increasing total energy consumption and leakage energy consumption, and achieve the effect of realizing design and low design

Active Publication Date: 2017-11-28
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] It can be seen that the delay is inversely proportional to the leakage current, and has a negative exponential relationship with the voltage, so as the power supply voltage drops, the delay increases rapidly, and the leakage energy consumption will instead increase and even lead to an increase in total energy consumption.

Method used

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  • Design method suitable for near-threshold and sub-threshold low electric leakage standard cell
  • Design method suitable for near-threshold and sub-threshold low electric leakage standard cell
  • Design method suitable for near-threshold and sub-threshold low electric leakage standard cell

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Embodiment

[0047] Taking the standard CMOS 0.18 micron process, power supply voltage VDD=0.4V, two-input NAND gate NAND2 unit as an example, the steps of unit size design are described in detail below:

[0048] 1. Select the minimum size tube W / L=220n / 180n as the standard size tube, and build an inverter based on the standard size tube, and obtain the leakage current when the input is low level and high level respectively I L,normn = 9.519p and I L,normp =0.7511p, then (I L,n / I L,p ) init =12.67.

[0049] 2. Use the NMOS and PMOS of the standard size to build the NAND2 structure, such as figure 2 shown. Let "0" represent a low level, and "1" represent a high level, then the leakage current of the two-input NAND gate NAND2 unit in the four states of input AB=00, 01, 10, and 11 is 0.5I respectively L,n , I L,n , I L,n and 2I L,p , then I L =0.25(0.5I L,n +I L,n +I L,n +2I L,p ) = 0.625I L,n +0.5I L,p , get λ n =0.625,λ p = 0.5, so λ n / λ p =1.25; when the two-input NA...

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Abstract

The invention discloses a design method suitable for a near-threshold and sub-threshold low electric leakage standard cell, and belongs to the technical field of digital integrated circuits. The design method comprises selecting standard devices of predetermined dimensions to build an inverter and calculating N / P electric leakage ratios of the standard devices; building a standard cell circuit and dividing leakage current and time delay of the standard cell circuit from sources thereof, calculating and obtaining N / P electric leakage coefficient ratios and N / P time delay coefficient ratios of the standard cell circuit, and therefore obtaining the optimal N / P electric leakage ratio of the standard cell circuit with minimum electric leakage energy consumption; and calculating adjusting parameters according to the N / P electric leakage ratios of the standard devices and the optimal N / P electric leakage ratio of the standard cell circuit, designing dimensions according to the adjusting parameters, and obtaining the optimal dimensions of NMOS transistors and PMOS transistors forming the standard cell circuit when the electric leakage energy consumption is minimum. The standard cell designed according to the method has low electric leakage characteristics, and therefore low-power digital circuits can be designed.

Description

technical field [0001] The invention relates to the technical field of digital integrated circuits, in particular to a design method for low-leakage standard cells suitable for near-threshold and sub-threshold. Background technique [0002] Digital integrated circuit semi-custom design is divided into two types based on standard cell library and gate array. Digital integrated circuit design based on standard cell refers to realizing the required circuit design by reusing the standard cells in the digital standard cell library. , the standard cell library contains basic logic units and some functional units required in circuit design, such as basic gate circuits, multi-way switches, flip-flops, full adders, encoders, etc. The standard cell library is designed and realized through the full custom design method according to the principle of the best design. It has been designed before the specific circuit design, which greatly reduces the cost and cycle of circuit design. But ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/30
Inventor 贺雅娟史兴荣张子骥张岱南衣溪琳何进张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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