Ring gate III-V quantum well transistor and germanium junctionless transistor and manufacturing method thereof

Abstract

The invention provides a ring gate III-V quantum well transistor and a germanium junctionless transistor and a manufacturing method thereof. The device comprises the III-V quantum well transistor and the germanium junctionless transistor. The III-V quantum well transistor comprises a first Ge band structure, an N-type InGaAs layer and an N+ type InGaAs layer. A first ring trench, a semiconductor barrier layer, a first high-K dielectric layer and a first metal gate are formed in the N+ type InGaAs layer. The germanium junctionless transistor comprises a second Ge band structure and a P+ type Ge layer. A second ring trench, a second high-K dielectric layer and a second metal gate are formed in the P+ type Ge layer. The method for effective integration of the ring gate III-V quantum well transistor and the germanium junctionless transistor is provided. Compared with the planar structure, the gate control capacity and the device driving capacity can be greatly enhanced by the ring gate III-V quantum well transistor and the germanium junctionless transistor so that the parasitic capacitance can be reduced and the device carrier mobility can be greatly enhanced.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a ring-gate III-V quantum well transistor and a germanium junction-free transistor and a manufacturing method thereof. Background technique [0002] Today, most integrated circuits are based on silicon. However, with the gradual reduction of the feature size of integrated circuits, the existing bulk silicon materials and processes are approaching their physical limits and encounter severe challenges. Below the 32nm technology node, especially below 22nm, the structure and materials of transistors will face more challenges. New technologies must be adopted to improve performance (new materials, new structures and new processes). Among them, the introduction of new channel materials is the main innovative approach. Studies have shown that Ge has higher hole mobility, and III-V semiconductor materials (such as GaAs, InP, InGaAs, InAs, and GaSb) have high...

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Problems solved by technology

[0002] Today, most integrated circuits are based on silicon. However, with the gradual reduction of integrated circuit feature size, existing bulk silicon materials and processes are approaching their physical limits and encounter severe challenges.

Below the 32nm technology node, especially below 22nm, the structure and materials of transistors will face more challenges

[0004] In the patent No. US8884363B2, a silicon nanowire transistor with a gate-around structure is disclosed. The main content is to form a silicon nanowire by patterning the top silicon and buried oxide layer of the SOI substrate, and then remove the supporting silicon nanowire transistor. part of the buried oxide layer of the wire, so that the position where the gate is to be prepared forms a suspended structure, and finally a ring-gate structure is fabricated based on the suspended structure. However, nanowires based on silicon materials are still affected by the physical limit of silicon itself, and it is difficult to operate at a lower temperature. Further improve the performance of the device under the technology node

In addition, the source-drain doping of the transistor produced in this patent is opposite to the channel doping, and the device channel is formed in the surface area of ​​the gate oxide layer. Due to the imperfection of the interface between the gate oxide layer and the semiconductor channel, the carriers are Scattering effects, resulting in reduced mobility and reduced reliability

[0005] In the publication of the patent publication number US20100164102A1, a method for manufacturing Ge nanobelts on a silicon fin structure is disclosed, which mainly forms Ge nanobelts through an oxidation and concentration process after growing GeSi on the top of a silicon fin structure. Since this process is to cover the GeSi material on the outside of the Si material, the concentration of Ge is relatively low, and the oxidation concentration process takes a long time, and the quality of the formed Ge nanobelts is also difficult to guarantee.

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