VLSI Standard Cell Layout Method Based on Electric Field Energy Modeling Technology

Abstract

The invention discloses a VLSI (Very Large Scale Integration) standard unit placement method based on an electric field energy modeling technology. The method establishes the electric field energy model of a problem, and a global density function and an analytical solution of a Poisson equation are utilized to solve a VLSI standard unit global placement problem. The method has the technical key point that: (1) analogy is carried out on the placement problem and a static electricity system, a unit is taken as an electric charge, original density constraint is converted into zero potential energy constraint, a differential equation is constructed, an explicit expression is solved for the differential equation to more accurately describe the potential energy constraint, then, a penalty function method is adopted to convert the wire length target and the potential energy constraint of the VLSI global placement into an unrestraint nonlinear placement problem, and a proper optimization technology is selected for optimization; and (2) different from a situation that a method for evenly dividing bin is used for obtaining a discrete density function value, the method disclosed by the invention is characterized in that the global density expression of the unit and the overlapping constraint of a whole placement area is calculated so as to more accurately describe the distribution situation of the unit on the placement area.

Description

technical field [0001] The invention relates to the technical field of VLSI physical design automation, in particular to a VLSI standard cell layout method based on electric field energy modeling technology. Background technique [0002] In the current VLSI layout, the scale of integrated circuits continues to increase and the requirements for technology are getting higher and higher, which puts forward higher requirements for the optimization goals and optimization methods of VLSI layout, and the quality of the layout results directly affects the quality of the entire chip. performance. With the rapid growth of the number of units on a chip, especially the widespread application of millions of gate chips, it poses a huge challenge to the automation of VLSI layout design. Therefore, it is of great significance to seek more efficient and practical integrated circuit layout algorithms [0003] Algorithms used to solve VLSI placement problems can be divided into the following...

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Problems solved by technology

[0005] However, the existing global layout methods based on analytical methods have the following two problems: (1) In the process of global layout, the method of uniformly dividing the layout area into bins is used for approximate calculation of density, because the density function is non-smooth , a smoothing approximation is also required

Therefore, there is a large error between the density constraint calculated after approximation and the actual density distribution, which is not a good reflection of the actual density of the layout, so that the quality of the layout cannot be guaranteed; (2) The existing layout tools use the Poisson equation to solve , but the numerical solution method is used, which also has a certain influence on the quality of the solution

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