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Convolutional Neural Networks on Programmable 2D Image Processors

A technology of convolutional neural network and image processor, which is applied in the field of convolutional neural network and can solve the problems of lack of a widely used programming environment

Active Publication Date: 2021-04-16
GOOGLE LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the use of custom-designed fixed-function circuits typically results in a limited set of tasks that the processor can perform
Thus, the second extreme (associated with the first) lacks a broadly general programming environment

Method used

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  • Convolutional Neural Networks on Programmable 2D Image Processors
  • Convolutional Neural Networks on Programmable 2D Image Processors
  • Convolutional Neural Networks on Programmable 2D Image Processors

Examples

Experimental program
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Embodiment Construction

[0028] a. The hardware structure and operation of the image processor

[0029] figure 1 An embodiment of an architecture 100 of an image processor implemented in hardware is depicted. The image processor may, for example, be targeted by a compiler that converts program code written for the virtual processor in an emulation environment into program code actually executed by the hardware processor. Such as figure 1 As shown, the architecture 100 includes a plurality of line buffer units 101_1 to 101_M (hereinafter referred to as "line buffer", "line buffer unit", etc.), and the plurality of line buffer units 101_1 to 101_M pass through a network 104 (such as a network on chip (NOC), including on-chip switch networks, on-chip ring networks, or other types of networks) interconnected to a plurality of template processor units 102_1 to 102_N (hereinafter referred to as "template processors", "template processor units", etc.) and Corresponding table generator units 103_1 to 103...

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PUM

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Abstract

A method is described that includes executing a convolutional neural network layer on an image processor with an array of execution channels and a two-dimensional shift register. Two-dimensional shift registers provide locally corresponding register spaces for execution channels. Execution of the convolutional neural network includes loading a plane of image data of a three-dimensional image data block into a two-dimensional shift register. Executing the convolutional neural network also includes performing a two-dimensional convolution of the plane of the image data with the array of coefficient values ​​by sequentially: multiplying corresponding pixels and coefficient values ​​simultaneously within an execution pass to produce an array of partial products; simultaneous in-channel summation of partial products and corresponding cumulative values ​​of partial products held in two-dimensional registers of different templates within the image data; and performing in-channel two-dimensional The alignment of the convolved values.

Description

technical field [0001] This description relates generally to image processing, and more specifically, to a convolutional neural network on a two-dimensional image processor. Background technique [0002] Image processing typically involves manipulating pixel values ​​organized into arrays. Here, the spatially organized two-dimensional array captures the two-dimensional nature of the image (additional dimensions may include time (eg, a series of two-dimensional images) and data type (eg, color)). Typically, the arrayed pixel values ​​are provided by a camera that produces a still image or a series of frames to capture a moving image. Traditional image processors typically fall into one of two extremes. [0003] The first extreme performs image processing tasks by executing software programs on a general purpose processor or a general purpose-like processor (eg, a general purpose processor with vector instruction enhancement). While the first extreme typically provides a hi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06T1/20G06N3/08
CPCG06N3/063G06T1/60G06T2200/28G06T2207/20084G06F9/3001G06F9/30032G06F9/30036G06F9/3885G06F9/3887G06N3/045G06T1/20G06F17/153G06T5/20G06N3/0464
Inventor O.沙查姆D.帕特森W.R.马克A.梅克斯纳D.F.芬切尔斯坦J.R.雷德格雷夫
Owner GOOGLE LLC