Convolutional Neural Networks on Programmable 2D Image Processors
A technology of convolutional neural network and image processor, which is applied in the field of convolutional neural network and can solve the problems of lack of a widely used programming environment
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[0028] a. The hardware structure and operation of the image processor
[0029] figure 1 An embodiment of an architecture 100 of an image processor implemented in hardware is depicted. The image processor may, for example, be targeted by a compiler that converts program code written for the virtual processor in an emulation environment into program code actually executed by the hardware processor. Such as figure 1 As shown, the architecture 100 includes a plurality of line buffer units 101_1 to 101_M (hereinafter referred to as "line buffer", "line buffer unit", etc.), and the plurality of line buffer units 101_1 to 101_M pass through a network 104 (such as a network on chip (NOC), including on-chip switch networks, on-chip ring networks, or other types of networks) interconnected to a plurality of template processor units 102_1 to 102_N (hereinafter referred to as "template processors", "template processor units", etc.) and Corresponding table generator units 103_1 to 103...
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