Wafer-level chip packaging structure and preparation method thereof

Abstract

The invention provides a wafer-level chip packaging structure and a preparation method thereof. The wafer-level chip packaging structure comprises semiconductor chips, a rewiring layer, soldering fluxprotruding blocks, a first protecting layer and a second protecting layer, wherein the rewiring layer comprises low-k medium layers and metal connection layers located inside and on the upper surfaces of the low-k medium layers, and the soldering flux protruding blocks are located on the upper surface of the rewiring layer and electrically connected with the metal connection layers; the first protecting layer is located on the peripheries of the semiconductor chips and the periphery of the rewiring layer, and the second protecting layer is located on the back faces of the semiconductor chip and on the bottom of the first protecting layer. The first protecting layer is formed on the peripheries of the semiconductor chips and the periphery of the rewiring layer, in this way, it can be effectively avoided that external vapor permeates into the low-k medium layer, and the low-k medium layer is more prone to breaking, the low-k medium layer can be stabilized, external force is prevented from damaging the low-k medium layer, no cracks occur on the low-k medium layer during cutting, and then the performance of the packaged chips is ensured.

Description

technical field [0001] The invention relates to a semiconductor package structure and a package method, in particular to a wafer-level chip package structure and a preparation method thereof. Background technique [0002] In the existing wafer-level chip packaging structure (WLCSP), in order to meet the needs of small-scale development, low-k dielectric layers (such as rewiring layers) will be used in the wafer-level chip packaging structure, and subsequent Laser cutting (lasersaw) or blade cutting (blade saw); but because the low-k dielectric layer is relatively brittle, especially when the low-k dielectric layer is exposed to the atmospheric environment, after the water vapor in the atmosphere enters the low-k dielectric layer, so that all The above-mentioned low-k dielectric layer will easily generate cracks in the subsequent cutting process, and the presence of cracks in the low-k dielectric layer will seriously affect the performance of the packaged chip. Contents of ...

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Problems solved by technology

[0003] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a wafer-level chip packaging structure and its preparation method, which is used to solve the problem in the prior art that cracks will be generated in the low-k dielectric layer during the cutting process. , which in turn affects the performance of the packaged chip

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