Chip scale package diode component with ultra-low forward voltage and manufacture method

Abstract

The present invention discloses a chip scale package diode component with an ultra-low forward voltage and a manufacture method. According to the diode component, all regions except a second electrodeare directly adopted as a first electrode, and / or the front surface and back surface of the first electrode are penetrated through perforation, and are conducting, and then cutting is performed, so that a chip scale package diode component finished product with a smaller size can be obtained. Since the first electrode is not required to be conducting through an epitaxial layer or a diffusion layer, and therefore, internal resistance can be avoided, a forward voltage can be lowered. With the manufacture method adopted, a manufacture process is simplified, quality can be improved, costs can bereduced, and the diode component can be lighter, shorter and smaller.

Description

technical field [0001] The present invention relates to a chip scale package (Chip Scale Package, CSP) diode element and a manufacturing method thereof. Plate (Silicon Wafer), Diffused Layer (Diffused), Diffused Silicon Wafer (Diffused Silicon Wafer). The finished diode element has the characteristics of ultra-low forward voltage (VF), and can simplify the manufacturing process, improve the quality, reduce the cost, and make the diode element lighter, thinner and shorter, and many other advantages. Background technique [0002] Generally, semiconductor materials are used to manufacture flip-chip (CSP) diode elements in grain size packages (CSP), including epitaxial wafers (EPI Wafer) and diffused silicon wafers (Diffused Silicon Wafer). The epitaxial wafer includes a substrate (Substrate) on the back side and an epitaxial layer (Epitaxy) on the front side. The diffused silicon wafer is to set a diffused layer (Diffused) on the front and back of a layer of silicon material,...

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Problems solved by technology

[0011] 1. The original purpose of the epitaxial / diffusion layer of the N pole is to allow electrons to pass through the N pole region at a lower internal resistance when the current is forward-conducting, but the epitaxial / diffusion layer itself will generate additional internal resistance. Therefore, the forward voltage (VF) is still high

[0012] 2. The epitaxial / diffusion layer for conduction is made by means of yellow light, etching, ion implantation or diffusion on the position of the substrate or diffused silicon crystal plate relative to the N pole. The process is long and the cost is high

[0013] 3. The area other than the P and N poles is idle and unused due to the setting of the guard ring and the insulating protective layer, and the forward voltage during forward conduction will also be high

[0014] 4. The cutting line is around the periphery of the P pole and the N pole. When cutting the components, the P pole and the N pole have the problem of peripheral cracking (CHIPPING & CRACK) at the same time, which seriously affects the quality stability of the finished product of the diode element.

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