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Method for Compensating Wafer Stress in 3d NAND Hybrid Bonding Process

A hybrid bond and wafer technology, applied in the manufacture of electrical components, circuits, semiconductor/solid-state devices, etc., can solve the problems of interface dislocation, uneven deformation, bonding failure, etc., to reduce the dislocation, improve the bonding power, Avoid damaging effects

Active Publication Date: 2018-11-13
YANGTZE MEMORY TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Since there are at least two materials with different expansion coefficients on the bonding interface, the metal and insulator on the bonding interface of the wafer will produce different degrees of stress under a certain temperature during the bonding process. Deformation, i.e. non-uniform deformation, resulting in interfacial misalignment at the bonding interface and ultimately bond failure

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  • Method for Compensating Wafer Stress in 3d NAND Hybrid Bonding Process

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Embodiment Construction

[0033] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0034] In the semiconductor manufacturing process, a wafer 1 is provided first, at this stage, the wafer 1 is flat, however when deep trench capacitors are formed on the front side of the wafer 1, the material of the deep trench capacitors is deposited under high temperature conditions And has a different coefficient of thermal expansion from the wafer 1 . When wafer 1 cools, the material filling the deep trench capacitors shrinks ...

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Abstract

The invention provides a method of compensating wafer stress in a 3D NAND hybrid bonding process. The method comprises: depositing a photoresist layer on a front surface of a 3D NAND wafer; depositinga tension film on the backside of the 3D NAND wafer; removing the photoresist layer and carrying out bonding of the 3D NAND wafer with a CMOS chip; and then carrying out roughened removing on the tension film at the back of the 3D NAND wafer. With the method provided by the invention, the wafer tolerance between the 3D NAND wafer and the COMS chip is controlled to be in a range of + / -30 microns,so that offset occurrence during bonding is reduced, the offset is controlled to be in a range of 150nm, and the bonding success rate is increased. Because the photoresist layer is formed on the frontside of the 3D NAND wafer, the damage of the 3D NAND wafer during the whole bonding process is avoided.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for compensating wafer stress in a 3D NAND hybrid bonding process. Background technique [0002] With the increasing demand for integration and storage capacity, 3D (three-dimensional) NAND memory has emerged. 3D NAND memory is a new type of product based on planar NAND memory. The main feature of this product is to convert the planar result into a three-dimensional structure, which greatly saves the silicon chip area, reduces manufacturing costs, and increases storage capacity. In the 3D NAND memory structure, the stacked 3D NAND memory structure is realized by stacking multiple layers of data storage units vertically. However, other circuits such as decoder, page buffer and latch ), etc. These peripheral circuits are all formed by CMOS devices, and the process of CMOS devices cannot be integrated with 3D NAND devices. Currently, 3D NAND memory arrays and pe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/18
CPCH01L21/185
Inventor 陶谦胡禺石吕震宇陈俊朱继锋肖莉红戴晓望姚兰
Owner YANGTZE MEMORY TECH CO LTD
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