Preparation method of metal gate

Abstract

The invention relates to a metal gate preparation method comprising the following steps: providing a semiconductor substrate, wherein the semiconductor substrate has a first zone and a second zone mutually separated, the first zone has a first dummy grid located on the semiconductor substrate surface, the second zone has a second dummy grid arranged on the semiconductor substrate surface, and an etching stop layer and an interlayer dielectric layer used for covering the first and second dummy grids are formed in order on the semiconductor substrate surface; etching the interlayer dielectric layer and the etching stop layer so as to expose top walls of the first and second dummy grids; back-etching the interlayer dielectric layer and the etching stop layer so as to expose partial side wallsof the first and second dummy grids; removing the first dummy grid so as to form the first groove, and filling the first metal gate in the first groove; removing the second dummy grid so as to form the second groove, and filling the second metal gate into the second groove. The method can reduce the first groove deep-width ratio, can enlarge the first metal gate process window, thus improving thefilling capacity.

Description

Technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method for preparing a metal gate. Background technique [0002] In the preparation of CMOS transistor devices and circuits, with the development of CMOS integrated circuit manufacturing process and the shrinking of key dimensions, due to SiO 2 The reduction of the dielectric thickness of the gate oxide layer increases the gate leakage current. At the same time, in order to avoid the depletion effect of the polysilicon gate, the HKMG (high k metal gate) process has become the mainstream, especially for process nodes below 28 nm. [0003] The commonly used HKMG process is gate last, but high k can be divided into high k last and high k first. In addition, since the threshold voltages of NMOS and PMOS are different, NMOS and PMOS need to use different work function adjustment layers. The formation process of metal gate can be divided into one-time...

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Problems solved by technology

[0005] The purpose of the present invention is to provide a method for preparing metal gates, which solves the problem of difficulty in filling metal gates in the prior art

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