A double-gate three-dimensional memory and its manufacturing method

Abstract

The embodiment of the present invention provides a double-gate three-dimensional memory and its manufacturing method. The three-dimensional memory includes: TSG and memory cells, and two channels are opened in the three-dimensional memory, and a doped channel is formed on each channel. plugs, and a gate structure is arranged between the two doped plugs, and the gate structure insulates the two doped plugs from each other. It can be seen that in this solution, there is a doped plug on each channel, so the current resistance can be reduced and the current channel can be improved. In addition, in this solution, by increasing the number of doped plugs, only one TSG is needed, and the problem of excessive threshold voltage swing generated between two TSGs is avoided. Moreover, since the current channel is improved in this solution, there is no boron implantation in the channel, thereby avoiding the problem of threshold voltage interference of the memory device caused by high-concentration doping. In addition, since the three-dimensional memory in this solution only includes one TSG, the density of memory cells can be increased.

Description

technical field [0001] The invention relates to the field of flash memory, and more specifically, to a double-gate three-dimensional memory and a manufacturing method thereof. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the planar NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory is proposed. [0003] In the 3D NAND memory structure, in order to increase the current while reducing the bit line current, usually, the top gate structure is designed as figure 1 In the structure shown, the 3D NAND memory structure includes two TSGs (TSG1 and TSG2) in the same bit line, and in order to increase the threshold voltage between the two TSGs, bor...

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Problems solved by technology

However, the inventors found that the existing memory structure needs to occupy more memory cells because it includes two TSGs. In addition, the implantation of high-concentration boron will lead to random doping fluctuations in the memory device, which further leads to threshold voltage interference. , in addition, there will be a large threshold voltage swing between the two TSGs, which will affect the performance of the device

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