A phase-locked loop self-calibration circuit

Abstract

The invention discloses a self-calibration circuit of a phase-locked loop (abbreviated as PLL), which comprises: a first counter counts the output clock of a crystal oscillator (abbreviated as XTAL); a second counter counts the frequency division clock of a voltage-controlled oscillator (abbreviated as VCO). counting; the binary search circuit outputs the switched capacitor control word of the LC oscillator corresponding to the preset frequency point; the look-up table circuit outputs the difference value of the switched capacitor control word between the target frequency point and the center frequency point; the fine-tuning control circuit is based on the binary search circuit , the look-up table circuit and the analog comparator output to obtain the switch capacitor array control word corresponding to the target frequency. The invention controls the capacitance value of the switched capacitor array in the inductor-capacitor oscillator through a digital circuit, expands the frequency tuning curve from one to multiple, saves the control word of the switched capacitor array at the center frequency point and the target frequency point and the switched capacitor at the center frequency point The difference value of the array control word realizes fast locking of the phase-locked loop only by fine-tuning when the frequency point is switched.

Description

technical field [0001] The invention relates to a self-calibration circuit of a phase-locked loop in integrated circuit design, which is mainly used for fast self-calibration of the phase-locked loop in multiple frequency tuning curves under each PVT. Background technique [0002] Phase-locked loops are widely used in frequency modulation systems, and their locking time is one of the key performance indicators for evaluating phase-locked loops. [0003] At present, the structure to reduce the lock time includes increasing the initial charge injection of the charge pump and dynamically adjusting the bandwidth of the loop filter. Dynamically adjust the bandwidth. When the phase error is small, the jitter performance can be improved by reducing the bandwidth. When the phase error is large, the locking speed can be accelerated by increasing the bandwidth; however, the phase error only indicates the degree of lag or lead of the phase, and does not represent the frequency. Theref...

AI Technical Summary

Problems solved by technology

Dynamically adjust the bandwidth. When the phase error is small, the jitter performance can be improved by reducing the bandwidth. When the phase error is large, the locking speed can be accelerated by increasing the bandwidth; however, the phase error only indicates the degree of lag or lead of the phase, and does not represent the frequency. Therefore, during the locking process, inconsistent changes in phase error and frequency error will lead to incorrect adjustment of bandwidth, which will affect the locking time

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