Memory and forming method thereof
A memory and conformal technology, which is applied in the manufacture of electric solid-state devices, semiconductor devices, and semiconductor/solid-state devices, etc., and can solve the problems of large coupling capacitance of the bit line conductive layer and prone to crosstalk.
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Embodiment 1
[0082] Figure 1a is a top view of a memory in Embodiment 1 of the present invention, figure 2 for Figure 1a Shown is a sectional view of the memory in Embodiment 1 of the present invention along the aa' and bb' directions. It should be noted that, Figure 1a and Figure 1b The structure of the memory in this embodiment is only schematically shown, and in order to more clearly highlight the core idea of the present invention, only some components are listed and other components are omitted, for example Figure 1a and Figure 1b Only the positional relationship between the storage active area of the memory and the bit line is indicated.
[0083] combine Figure 1a and Figure 1b As shown, the memory includes:
[0084] A substrate 10, on which a device region 100 is defined;
[0085] A plurality of bit line conduction layers 110 are formed on the device region 100 on the substrate 10, and the plurality of bit line conduction layers 110 extend in the same direction (for...
Embodiment 2
[0108] The difference from Embodiment 1 is that the bit line separation interlayer in this embodiment includes a low-K dielectric layer, and the dielectric constant of the low-K dielectric layer is smaller than that of the bit line conformal layer and the bit line masking layer.
[0109] image 3 It is a schematic structural diagram of the memory in Embodiment 2 of the present invention, such as image 3 As shown, the low-K dielectric layer of the bit line separation interlayer 130' covers the part of the bit line conformal layer 120' attached to the side wall of the bit line conductive layer 110, so as to indirectly cover the sidewalls of the bit line conductive layer 110 . And, the bit line masking layer 140' covers the low-K dielectric layer of the bit line separation interlayer 130', so that the bit line conformal layer 120' is attached to the side wall of the bit line conductive layer 110 part above, the part of the low-K dielectric layer of the bit line separation inte...
Embodiment 3
[0120] Figure 4 It is a schematic flowchart of a method for forming a memory in Embodiment 3 of the present invention, Figure 5a ~ Figure 5b , Figure 6 ~ Figure 8 It is a schematic structural diagram of the memory forming method in the third embodiment of the present invention during its preparation process. The method for forming the output memory in this embodiment will be described in detail below with reference to the accompanying drawings.
[0121] In step S100, refer to Figure 5a and Figure 5b As shown, a substrate 10 is provided, and a device region 100 is defined on the substrate 10, and a plurality of bit line conductive layers 110 are formed on the device region 100 on the substrate 10, and a plurality of the The bit line conductive layer 110 extends along the same direction (eg Figure 5a shown extending in the X direction).
[0122] Further, a peripheral region 200 located on the periphery of the device region 100 is also defined on the substrate 10 . A...
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