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Small point number FFT rotation factor complex multiplication accelerator

A twiddle factor and complex multiplication technology, applied in electrical digital data processing, digital data processing components, instruments, etc., can solve problems such as high hardware overhead and slow calculation speed, and achieve high calculation speed, circuit performance, and hardware reduction. The effect of resource consumption

Inactive Publication Date: 2018-04-13
TIANJIN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] The purpose of the present invention is to design an efficient twiddle factor complex multiplication accelerator to solve the problems of large hardware overhead and slow calculation speed of complex multipliers in most FFTs, thereby improving system performance

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  • Small point number FFT rotation factor complex multiplication accelerator
  • Small point number FFT rotation factor complex multiplication accelerator
  • Small point number FFT rotation factor complex multiplication accelerator

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Embodiment Construction

[0025] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0026] The invention relates to a circuit structure design of a small point number (8 points, 16 points, 32 points) FFT twiddle factor complex multiplication accelerator. The complex multiplication of the twiddle factor in the known FFT is as follows:

[0027] (x re +jx im )(cosa-jsina)=(x re cosa+x im sina)+j(x im cosa-x re sina)

[0028] where (x re +j x im ) is the input data; (cosa+j sina) is the rotation factor. All twiddle factors need to be calculated in advance and stored in ROM for multiplication calculation, so the characteristic of multiplication is that a multiplier is known. According to this feature, the present invention designs a constant-complex multiplication accelerator to replace the traditional complex multiplier, and the constant coefficient of the constant-complex multiplication accelerator is the twiddle factor.

[0029] In addition...

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Abstract

The invention relates to a small point number FFT rotation factor complex multiplication accelerator. A process of the accelerator comprises the steps of left shifting a whole decimal of each rotationfactor for 6 bits; performing round-off operation on each shifted binary number to enable the binary number to be approximate to an integer; right shifting each integer and restoring the integer to an original decimal; performing circuit design on each integer in a shifting and adding manner, wherein each integer corresponds to an integer constant multiplier; multiplexing same parts in all integer constant multiplier circuits by utilizing an alternative multiplexer to further reduce an adder quantity; and inserting a register in each adder to perform pipeline processing.

Description

technical field [0001] The invention belongs to the design category of Very Large Scale Integration (VLSI for short), and proposes a VLSI structure of a complex multiplication accelerator for twiddle factors in a small-point Fast Fourier Transform (FFT for short). Background technique [0002] Fast Fourier transform is a fast implementation form of discrete Fourier transform (DFT for short), and it is also one of the important algorithms in the field of digital signal processing. It is widely used in various real-time time-frequency conversion processors. . Due to its large amount of calculation, in order to meet the needs of real-time processing, hardware circuits must be used to improve the calculation speed; and the complex multiplication of twiddle factors is one of the most important calculation units in FFT, because it occupies 70% of the hardware resources required by FFT. %, and determines the calculation speed of the overall FFT architecture, so designing an effici...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/48
CPCG06F7/4812
Inventor 梁煜沈耀坡张为
Owner TIANJIN UNIV