FPGA-based polling system distinguishing priority
A technology of priority and information grouping, applied in CAD circuit design, special data processing applications, instruments, etc., can solve problems such as different service quality requirements
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[0023] The specific implementation of the system will be described below in conjunction with the working principle of the present invention.
[0024] The present invention combines the Verilog HDL hardware description language and the principle diagram method to realize the redesign of FPGA, flexibly control the scheduling mode of the polling system, and control the server to send the information of each site according to the strategy of full service of the central site and threshold service of the common site, and the control system Every time a common site is served, it is necessary to check whether the central site needs service again, so that the service quality of the central site is guaranteed.
[0025] A simple polling process can be expressed as the information packet arrival process of each station, the information packet service process and the polling conversion process of adjacent stations. Therefore, the main realization content of the invention is: use the princip...
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