A through-silicon via test structure and test method thereof

Abstract

The invention provides a silicon through hole testing structure and method, and the structure comprises a semiconductor substrate which is of a first conductive type; a silicon through hole which is located in the semiconductor substrate and comprises a through hole main body and an insulating layer from the inside to the outside; a first heavy doped region which is of a second conductive type, islocated in the semiconductor substrate and is set around the silicon through hole; a second heavy doped region which is of a first conductive type, is located in the semiconductor substrate and is set outside the first heavy doped region at intervals; and an interconnection structure which is electrically connected with the silicon through hole, the first heavy doped region and the second heavy doped region. The structure can measure whether there is a leaked current or not to judge whether an insulating layer is complete or not, and also can measure a capacitance value to judge whether the depth of the silicon through hole reaches a standard value or not. Moreover, the leaked current and the capacitance value are more accurate and sensitive, thereby achieving the more accurate testing ofwhether the insulating layer is complete or not and whether the depth of the silicon through hole reaches the standard value or not.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a through-silicon via test structure and a test method thereof. Background technique [0002] With the continuous development of semiconductor technology, the feature size of semiconductor devices has become very small. It is becoming more and more difficult to increase the number of semiconductor devices in a two-dimensional packaging structure. Therefore, three-dimensional packaging has become a method that can effectively improve chip integration. degree method. Current three-dimensional packaging includes die stacking based on gold wire bonding, package stacking and three-dimensional stacking based on through silicon vias (Through Silicon Via, TSV). Among them, the three-dimensional stacking technology using through-silicon vias has the following three advantages: (1) high-density integration; (2) greatly shortening the length of electrical interconnections, which can...

AI Technical Summary

Problems solved by technology

There is a method for measuring the depth of TSVs in the current technology, but the method needs to form a microfluidic pressure sensing device on the surface of TSVs for detection, the test structure is relatively complicated, the detection is cumbersome, and the test cost is high

[0005] There are other TSV test structures in the current process, which can judge whether the insulating layer is complete by measuring whether there is leakage current, or judge whether the depth of the TSV reaches the standard value by measuring the capacitance value, but in the above In the structure and test method, the test total capacitance Ct includes oxide capacitance and depletion capacitance, so the test total capacitance Ct is smaller than the oxide capacitance, so that the test sensitivity is not accurate enough

Furthermore, for the leakage current test, if there are defects in the depletion layer, the leakage current will also be blocked, so that the leakage current test sensitivity is reduced or invalid

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