30results about How to "No additional process steps required" patented technology

The invention discloses a die bonding method used for a GaAs MMIC thinning technology. The method comprises the steps of: evenly coating an electron beam photoresist on the front surface of a substrate and pasting the surface of the substrate to a quartz holder with liquid wax, wherein the liquid wax is composed of a certain amount of Crystalbond 509 strong adhesive and acetone capable of dissolving the amount of the Crystalbond 509 strong adhesive. According to the invention, the liquid wax of a special formula is used instead of conventional high-temperature wax, and in the usage environment, organic matters, which are difficult to remove and generated by mutual dissolution of the photoresist and the high-temperature wax, are prevented without adding other barrier layers; secondly, both the liquid wax and the photoresist are freely soluble in acetone, so that the problem in the conventional technology, that glue removing is slow and difficult when the high-temperature wax is used in the die bonding process, is solved; in addition, good adhesiveness is achieved between the substrate and the quartz holder, and the fragment problem in the polishing and thinning processes is effectively solved.

The present invention relates to a high-bandwidth bending insensitive multimode optical fiber. The high-bandwidth bending insensitive multimode optical fiber comprises a core layer and claddings surrounding the core layer. The refractive index cross section of the core layer is in the shape of a parabola. The high-bandwidth bending insensitive multimode optical fiber is characterized in that the claddings include an inner cladding, a first recessed cladding, a second recessed cladding and an outer cladding which are distributed sequentially from inside to outside; the unilateral radial width (R2-R1) of the inner cladding ranges from 1 to 3 microns, and the relative refractive index difference delta 2 of the inner cladding ranges from -0.2% to 0.05%; the unilateral radial width (R3-R2) of the first recessed cladding ranges from 3 to 8 microns, and the relative refractive index difference delta 3 of the first recessed cladding ranges from -0.9% to 0.3%; the unilateral radial width (R4-R3) of the second recessed cladding ranges from 6 to 30 microns, and R4 is smaller than or equal to 58 microns, and the relative refractive index difference delta 4 of the second recessed cladding ranges from -0.15% to 0.01%; and the radius R5 of the outer cladding ranges from 60 to 65 microns, and the relative refractive index difference delta 5 of the outer cladding ranges from -0.15% to 0.15%. The optical fiber of the invention has the advantages of reasonable material composition and structural design, convenient process control, improved and reduced inner stress distribution, enhanced bending resistance and increased bandwidth.

The invention discloses an optical waveguide resonant cavity with a high polarization extinction ratio based on an inclined waveguide grating structure. An optical waveguide chip body is provided with an input / output light channel and a resonant ring, wherein the two ends of the input / output light channel are positioned on the edge of an optical waveguide chip; the resonant ring is connected with the input / output light channel through an input / output coupler, so that an optical waveguide resonant cavity is formed; an inclined waveguide grating is etched on the resonant ring; the included angle between the reflecting interface of the inclined waveguide grating and a light ray transmitting direction is shown in the specifications, wherein n1 is the refractive index of an optical waveguide chip cladding part, and n2 is the refractive index of an optical waveguide chip sandwich layer part; and the etching depth of the inclined waveguide grating is more than zero and less than the thickness of an optical waveguide chip sandwich layer. According to the optical waveguide resonant cavity, the defect of the absence of an effective means for suppressing polarization fluctuation noise for the optical waveguide resonant cavity is overcome; and the optical waveguide resonant cavity can be applied in other fields of resonant micro-optical gyroscopes and the like, and has important scientific meaning and application value.

The invention provides an anti-adhesion radio frequency mechanical switch and a preparation method thereof. The anti-adhesion radio frequency mechanical switch includes a substrate; a coplanar waveguide structure is arranged on the substrate for transmitting radio frequency and microwave signal; a cantilever beam structure, including a cantilever beam, an inductance array and a contact; one end of the cantilever beam is connected to the coplanar waveguide structure through a bracket, and the other end of the cantilever beam is provided with a contact; the inductance array is arranged on the on the cantilever beam; the driving structure includes an inductor and a pad, and the inductor is arranged on the substrate; the inductor is connected to the pad through a metal wire. The present invention realizes that the radio frequency mechanical switch actively breaks away from the adhesion state through the cantilever beam structure, and avoids the switch failure problem caused by the contact adhesion problem of the radio frequency mechanical switch with the increase of power during the use process.

The invention discloses a trench-type super-junction device layout structure. A plurality of grooves for forming a column in each grain, the adjacent parallel grooves as a groove array, the array direction of the grooves adjacent to each other perpendicular to the array. The present application also discloses a method of manufacturing a trench-type super junction devices, it has formed a super junction structure having two or more of an array of channels in each grain, each groove by adjacent and parallel array composed of grooves, the grooves adjacent to the array direction of the array perpendicular to each other; said method comprising the ion implantation process is formed to cover all the grooves of the array ion-implanted region, ion-implanted region is formed at least one groove parallel to the array and at least another array of channels perpendicular to; final on all array of channels are formed super junction devices. This application is arranged perpendicular to each other by adjacent grains or cell array of channels, and to counteract the stress of deep trenches etched, and overcome the dislocations and other defects.

The invention discloses a graphene-based tunneling transistor, an inverter and a preparation method thereof. The graphene tunneling transistor includes a source, a gate, a drain, a graphene film, a semiconductor or metal substrate, and a tunneling layer , drain insulating layer, gate insulating layer, graphene passivation layer and DC bias voltage source; the source electrode is connected to the silicon substrate, the drain electrode is connected to the graphene film, and there is a layer of tunneling between the graphene and the substrate layer, the gate is on top of the electron tunneling section. If the work function of the semiconductor or metal substrate is small, the metal with a large work function is selected for the drain, and the device is n-type; otherwise, the metal with a large work function is used for the drain, and the device is p-type. The drain of the p-type tube is connected to a high potential, and the source of the n-type tube is connected to a low potential. A novel graphene tunneling transistor structure realizes a digital logic inverter with high response rate and low static power consumption.

The invention provides a silicon through hole testing structure and method, and the structure comprises a semiconductor substrate which is of a first conductive type; a silicon through hole which is located in the semiconductor substrate and comprises a through hole main body and an insulating layer from the inside to the outside; a first heavy doped region which is of a second conductive type, islocated in the semiconductor substrate and is set around the silicon through hole; a second heavy doped region which is of a first conductive type, is located in the semiconductor substrate and is set outside the first heavy doped region at intervals; and an interconnection structure which is electrically connected with the silicon through hole, the first heavy doped region and the second heavy doped region. The structure can measure whether there is a leaked current or not to judge whether an insulating layer is complete or not, and also can measure a capacitance value to judge whether the depth of the silicon through hole reaches a standard value or not. Moreover, the leaked current and the capacitance value are more accurate and sensitive, thereby achieving the more accurate testing ofwhether the insulating layer is complete or not and whether the depth of the silicon through hole reaches the standard value or not.

An area array sensor device and its forming method, the area array sensor device includes: a drive circuit and a sensor circuit, the drive circuit and the sensor circuit are formed on the same substrate surface, and the sensor circuit includes a pixel unit array composed of pixel units and the driving line connected to the pixel unit, the output terminal of the driving circuit is connected to the driving line of the sensor circuit, the driving circuit includes a first transistor, and the pixel unit includes a second transistor; the first transistor includes The first shielding layer, the second transistor includes a second shielding layer. In the area array sensor device of the technical solution of the present invention, the components of the drive circuit and the sensor circuit can be manufactured on the same substrate, which reduces the occupied area and improves the reliability, and the formation process can be carried out synchronously without adding additional process steps.

The invention discloses stamping equipment used for mechanical stamped parts, and relates to stamping equipment. The stamping equipment comprises a frame, a hydraulic oil cylinder is fixedly connectedto the top of the frame, a connecting rod is fixedly connected to the output end of the hydraulic oil cylinder, a stamping upper die is fixedly connected to the bottom of the connecting rod through ahorizontal seat, the connecting rod is made of a nonferromagnetic material, a sliding groove is formed in the middle of the connecting rod, a magnet is slidably connected to the inner side of the sliding groove, and a transmission rod is fixedly connected to the middle of the front side of the magnet. A swing rod is rotationally connected to the right side of the connecting rod through a verticalrod, a transmission groove is fixedly connected to the left side of the swing rod, the transmission groove sleeves the outer side of the transmission rod, a limiting stop rod is fixedly connected tothe right side of the frame, and the limiting stop rod is matched with the right end of the swing rod. The stamping equipment is simple in structure and convenient to use, the stamped parts are stamped through hydraulic driving during use, the machined stamped parts can be effectively and rapidly discharged through the up-and-down movement of a plunger rod after stamping is completed, and processsteps do not need to be added.

The invention provides a light-emitting diode (LED) chip with a capacitance structure and a preparation method thereof. The LED chip comprises an N-type semiconductor layer, a multi-quantum well light-emitting layer, a P-type semiconductor layer, an N electrode and a P electrode, wherein the N electrode is electrically connected with the N-type semiconductor layer, the P electrode is electrically connected with the P-type semiconductor layer, the LED chip is electrically connected with the capacitance structure, the capacitance structure comprises a first conductive layer, a second conductive layer and a dielectric material layer, the first conductive layer and the second conductive layer are parallel to each other and are arranged at intervals, the dielectric material layer is arranged between the first conductive layer and the second conductive layer, the first conductive layer is electrically connected with the P electrode, the second conductive layer is electrically connected with the N electrode, and the first conductive layer and the second conductive layer in the capacitance structure and the P electrode and the N electrode of the LED chip are arranged in parallel. By additionally arranging the capacitance structure on the LED chip, the capacitance structure can play a protection role on the LED chip, ripple can be filtered, surge impact is prevented, and the reliability of the LED chip is improved.

The present invention relates to a memory structure and a forming method thereof. The memory structure includes: a first base, including: a substrate layer and a storage layer, the substrate layer has a first surface and a second surface opposite to each other, and the storage layer is located on On the first surface of the substrate layer, the first substrate includes a pad area; a dielectric layer located on the second surface of the substrate layer; a solder pad located on the surface of the dielectric layer on the pad area; isolation The structure penetrates through the substrate layer, is located at the edge of the pad region, surrounds the substrate layer in the pad region, and is used to isolate the substrate layer in the pad region from the substrate layer around the isolation structure. In the memory structure of the present invention, the parasitic capacitance between the pad and the substrate layer is reduced, which is beneficial to improving memory performance.

A lateral insulated gate bipolar transistor with low turn-on overshoot current reduces the current peak value flowing through the device when the second gate pulse is turned on without reducing the current capability and withstand voltage capability. The semiconductor has: a buried oxygen on a P-type substrate, an N-type drift region on the buried oxygen, a P-type body region and an N-type buffer zone on it, and a P-type collector in the N-type buffer zone region, a field oxygen layer is provided above the N-type drift region, a P-type well region is provided in the P-type body region, a P-type emitter region and an emitter region are arranged in the P-type well region, and the inside of the above-mentioned 4 regions The boundary is synchronously invaginated to form a pinch-off region. The surface of the P-type body region is provided with a gate oxide layer, and the gate oxide layer is provided with a polysilicon gate electrode, and the polysilicon gate electrode is composed of the first gate electrode located above the surface of the P-type body region and the pinch-off region and the N-type drift region. Composed of the second grid electrode, the first grid electrode is connected to the first grid resistor, and the second grid electrode is connected to the second grid resistor.