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30results about How to "No additional process steps required" patented technology

RDL (radiological defense laboratory) technology-compatible inductive component and manufacture method

The invention relates to an RDL (radiological defense laboratory) technology-compatible inductive component and a manufacture method. The method is characterized by comprising the following steps of: using a thin film metal deposition technology on a silicon substrate and simultaneously forming a first layer metal interconnection transmission line and a shielding layer; carrying out the spin coating of a photosensitive medium layer, and developing in an exposure way, forming into a metal interconnection through hole, annealing, performing dry etching on plasmas to remove the developing remaining part, and filling the metal interconnection through hole with plated metal; forming a second layer metal interconnection transmission line and an inductance coil; forming an outermost layer metal through hole; and manufacturing an electrical inductor with the metal shielding layer under the condition that the original technological steps are not increased. The invention is compatible with the main-stream re-wiring technology in wafer level encapsulation, under the condition that the technological steps are not increased, the electrical inductor with the shielding layer can be manufactured at low cost, the substrate eddy current of the silicon substrate can be effectively cut off, the quality factor of the electric inductor can be improved, the series resistance of the electric inductor can be reduced, and the electromagnetic interference of the vortex current to a chip can be reduced.
Owner:SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI

Light-emitting diode (LED) chip with capacitance structure and preparation method thereof

The invention provides a light-emitting diode (LED) chip with a capacitance structure and a preparation method thereof. The LED chip comprises an N-type semiconductor layer, a multi-quantum well light-emitting layer, a P-type semiconductor layer, an N electrode and a P electrode, wherein the N electrode is electrically connected with the N-type semiconductor layer, the P electrode is electrically connected with the P-type semiconductor layer, the LED chip is electrically connected with the capacitance structure, the capacitance structure comprises a first conductive layer, a second conductive layer and a dielectric material layer, the first conductive layer and the second conductive layer are parallel to each other and are arranged at intervals, the dielectric material layer is arranged between the first conductive layer and the second conductive layer, the first conductive layer is electrically connected with the P electrode, the second conductive layer is electrically connected with the N electrode, and the first conductive layer and the second conductive layer in the capacitance structure and the P electrode and the N electrode of the LED chip are arranged in parallel. By additionally arranging the capacitance structure on the LED chip, the capacitance structure can play a protection role on the LED chip, ripple can be filtered, surge impact is prevented, and the reliability of the LED chip is improved.
Owner:FOCUS LIGHTINGS SCI & TECH

Moisture-absorbing and environment-protection type fabric

The invention discloses a moisture-absorbing and environment-protection type fabric. The moisture-absorbing and environment-protection type fabric is characterized by comprising the following raw materials in percentage by mass: 12 to 20% of hemp fiber, 10 to 26% of chinlon, 2 to 5% of fluon, and 6 to 14% of copper ammonia fiber, wherein color cotton and the chinlon are blended to form an inner layer of the moisture-absorbing and environment-protection type fabric; the hemp fiber and wool fiber are blended to form an isolation layer of the moisture-absorbing and environment-protection type fabric; the copper ammonia fiber and the fluon are blended to form a surface layer of the moisture-absorbing and environment-protection type fabric. The moisture-absorbing and environment-protection type fabric has the advantages that the fabric is light, thin and comfortable, the moisture-absorbing effect is good, and the moisture-absorbing, drying and heat-insulation effects are realized by utilizing different raw materials in different positions; if the moisture-absorbing and environment-protection type fabric is not worn after use, the moisture-absorbing and environment-protection type fabric can be automatically degraded after a period of time, so that the time and labor are saved, and the environment-protection effect is realized; the production cost is lower, the production technology is simple, any additional technological step is not needed, and the production efficiency is improved.
Owner:南通中兴多元复合钢管有限公司

High-bandwidth bending insensitive multimode optical fiber

The present invention relates to a high-bandwidth bending insensitive multimode optical fiber. The high-bandwidth bending insensitive multimode optical fiber comprises a core layer and claddings surrounding the core layer. The refractive index cross section of the core layer is in the shape of a parabola. The high-bandwidth bending insensitive multimode optical fiber is characterized in that the claddings include an inner cladding, a first recessed cladding, a second recessed cladding and an outer cladding which are distributed sequentially from inside to outside; the unilateral radial width (R2-R1) of the inner cladding ranges from 1 to 3 microns, and the relative refractive index difference delta 2 of the inner cladding ranges from -0.2% to 0.05%; the unilateral radial width (R3-R2) of the first recessed cladding ranges from 3 to 8 microns, and the relative refractive index difference delta 3 of the first recessed cladding ranges from -0.9% to 0.3%; the unilateral radial width (R4-R3) of the second recessed cladding ranges from 6 to 30 microns, and R4 is smaller than or equal to 58 microns, and the relative refractive index difference delta 4 of the second recessed cladding ranges from -0.15% to 0.01%; and the radius R5 of the outer cladding ranges from 60 to 65 microns, and the relative refractive index difference delta 5 of the outer cladding ranges from -0.15% to 0.15%. The optical fiber of the invention has the advantages of reasonable material composition and structural design, convenient process control, improved and reduced inner stress distribution, enhanced bending resistance and increased bandwidth.
Owner:YANGTZE OPTICAL FIBRE & CABLE CO LTD

High Bandwidth Bend Insensitive Multimode Fiber

The present invention relates to a high-bandwidth bending insensitive multimode optical fiber. The high-bandwidth bending insensitive multimode optical fiber comprises a core layer and claddings surrounding the core layer. The refractive index cross section of the core layer is in the shape of a parabola. The high-bandwidth bending insensitive multimode optical fiber is characterized in that the claddings include an inner cladding, a first recessed cladding, a second recessed cladding and an outer cladding which are distributed sequentially from inside to outside; the unilateral radial width (R2-R1) of the inner cladding ranges from 1 to 3 microns, and the relative refractive index difference delta 2 of the inner cladding ranges from -0.2% to 0.05%; the unilateral radial width (R3-R2) of the first recessed cladding ranges from 3 to 8 microns, and the relative refractive index difference delta 3 of the first recessed cladding ranges from -0.9% to 0.3%; the unilateral radial width (R4-R3) of the second recessed cladding ranges from 6 to 30 microns, and R4 is smaller than or equal to 58 microns, and the relative refractive index difference delta 4 of the second recessed cladding ranges from -0.15% to 0.01%; and the radius R5 of the outer cladding ranges from 60 to 65 microns, and the relative refractive index difference delta 5 of the outer cladding ranges from -0.15% to 0.15%. The optical fiber of the invention has the advantages of reasonable material composition and structural design, convenient process control, improved and reduced inner stress distribution, enhanced bending resistance and increased bandwidth.
Owner:YANGTZE OPTICAL FIBRE & CABLE CO LTD

Optical waveguide resonator with high polarization extinction ratio based on tilted waveguide grating structure

The invention discloses an optical waveguide resonant cavity with a high polarization extinction ratio based on an inclined waveguide grating structure. An optical waveguide chip body is provided with an input / output light channel and a resonant ring, wherein the two ends of the input / output light channel are positioned on the edge of an optical waveguide chip; the resonant ring is connected with the input / output light channel through an input / output coupler, so that an optical waveguide resonant cavity is formed; an inclined waveguide grating is etched on the resonant ring; the included angle between the reflecting interface of the inclined waveguide grating and a light ray transmitting direction is shown in the specifications, wherein n1 is the refractive index of an optical waveguide chip cladding part, and n2 is the refractive index of an optical waveguide chip sandwich layer part; and the etching depth of the inclined waveguide grating is more than zero and less than the thickness of an optical waveguide chip sandwich layer. According to the optical waveguide resonant cavity, the defect of the absence of an effective means for suppressing polarization fluctuation noise for the optical waveguide resonant cavity is overcome; and the optical waveguide resonant cavity can be applied in other fields of resonant micro-optical gyroscopes and the like, and has important scientific meaning and application value.
Owner:ZHEJIANG UNIV

A through-silicon via test structure and test method thereof

The invention provides a silicon through hole testing structure and method, and the structure comprises a semiconductor substrate which is of a first conductive type; a silicon through hole which is located in the semiconductor substrate and comprises a through hole main body and an insulating layer from the inside to the outside; a first heavy doped region which is of a second conductive type, islocated in the semiconductor substrate and is set around the silicon through hole; a second heavy doped region which is of a first conductive type, is located in the semiconductor substrate and is set outside the first heavy doped region at intervals; and an interconnection structure which is electrically connected with the silicon through hole, the first heavy doped region and the second heavy doped region. The structure can measure whether there is a leaked current or not to judge whether an insulating layer is complete or not, and also can measure a capacitance value to judge whether the depth of the silicon through hole reaches a standard value or not. Moreover, the leaked current and the capacitance value are more accurate and sensitive, thereby achieving the more accurate testing ofwhether the insulating layer is complete or not and whether the depth of the silicon through hole reaches the standard value or not.
Owner:SEMICON MFG INT (SHANGHAI) CORP +1

Phase inverter for tunneling transistor based on graphite, and preparation method thereof

The invention discloses a phase inverter for a tunneling transistor based on graphite, and a preparation method thereof. The graphene tunneling transistor comprises a source electrode, a grid electrode, a drain electrode, a graphene film, a semiconductor or metal substrate, a tunneling layer, a drain electrode insulating layer, a grid electrode insulating layer, a graphene passivation layer and adirect current bias voltage source, wherein the source electrode and a silicon substrate are connected, the drain electrode and the graphene film are connected, one tunneling layer is arranged betweenthe graphene and the substrate, and the grid electrode is arranged on the top of an electron tunneling part. If the work function of the semiconductor or metal substrate is small, the drain electrodeselects metal with a large work function, and the device is of an n type; and otherwise, the drain electrode adopts the metal with the large work function, and the device is of a p type. The p-type pipe drain electrode is connected with a high level, an n-type pipe source electrode is connected with a low level, the common grid electrode of two pipes serves as the input end of a circuit, and a p-type pipe source electrode and an n-type pipe drain electrode are connected to serve as the output end of the circuit. By use of the novel graphene tunneling transistor structure, a digital logic phase inverter with a high response rate and low static power consumption is realized.
Owner:SOUTHEAST UNIV

An endpoint monitoring method for backhole etching of high electron mobility transistors

The invention provides a terminal point monitoring method of high-electron-mobility transistor back hole etching. Two kinds of metal are alternatively grown on a wiring layer of a device right side technology so as to form a periodic metal layer. The periodic metal layer is located above a position of a back side through hole to be etched. The terminal point monitoring method comprises the following steps of S1, acquiring a real-time etching spectrum signal; S2, determining whether to generate a periodic spectrum signal; S3, if the periodic spectrum signal is generated, stopping etching after 30s over etching; and S4, if the periodic spectrum signal is not generated, repeatedly executing the step S2. In the invention, through a periodic lamination design wiring a periodic metal layer in a right side, an identification degree and sensitivity of a terminal point signal of a terminal point monitoring system are increased and accuracy and validity of terminal point decision are increased too; the method is especially suitable for silicon-carbide-based gallium nitride high-electron-mobility transistor back hole etching with an exposed area proportion which is not high (<2%); and technology reliability of back hole etching can be obviously improved and a high practical value is possessed.
Owner:CHENGDU HIWAFER SEMICON CO LTD

Trench gate type silicon-on-insulator lateral insulated gate bipolar transistor device

The invention discloses a trench gate type silicon-on-insulator transverse insulated gate bipolar transistor device. According to the device of the invention, buried oxide is arranged on a P-type substrate; an N-type drift region is arranged on the buried oxide; a P-type body region and an N-type buffer region are arranged on the N-type drift region; a P-type collector region is arranged in the N-type buffer region; a square-wave-shaped heavily-doped N-type emitter region and a square-wave-shaped heavily-doped P-type emitter region are arranged in the P-type body region side by side; and a first square-wave-shaped longitudinal trench and a second square-wave-shaped longitudinal trench are formed on two sides of the square-wave-shaped heavily-doped N-type emitter region and the square-wave-shaped heavily-doped P-type emitter region; the first longitudinal trench is provided with a first polycrystalline silicon layer wrapped by a voltage-withstanding medium; a portion of the second longitudinal trench, which is parallel to the heavily doped P-type collector region, is filled with a second polycrystalline silicon layer wrapped by a voltage-withstanding medium; and a portion of the second longitudinal trench, which is located in a direction from the heavily-doped N-type emitter region to the heavily-doped P-type collector region, is filled with a third polycrystalline silicon layerand an oxide block body, wherein the third polycrystalline silicon layer is wrapped by a voltage-withstanding medium, and the oxide block body is positioned above the third polycrystalline silicon layer; and the second polycrystalline silicon layer is connected with the third polycrystalline silicon layer.
Owner:SOUTHEAST UNIV

A stamping equipment for mechanical stamping parts

The invention discloses stamping equipment used for mechanical stamped parts, and relates to stamping equipment. The stamping equipment comprises a frame, a hydraulic oil cylinder is fixedly connectedto the top of the frame, a connecting rod is fixedly connected to the output end of the hydraulic oil cylinder, a stamping upper die is fixedly connected to the bottom of the connecting rod through ahorizontal seat, the connecting rod is made of a nonferromagnetic material, a sliding groove is formed in the middle of the connecting rod, a magnet is slidably connected to the inner side of the sliding groove, and a transmission rod is fixedly connected to the middle of the front side of the magnet. A swing rod is rotationally connected to the right side of the connecting rod through a verticalrod, a transmission groove is fixedly connected to the left side of the swing rod, the transmission groove sleeves the outer side of the transmission rod, a limiting stop rod is fixedly connected tothe right side of the frame, and the limiting stop rod is matched with the right end of the swing rod. The stamping equipment is simple in structure and convenient to use, the stamped parts are stamped through hydraulic driving during use, the machined stamped parts can be effectively and rapidly discharged through the up-and-down movement of a plunger rod after stamping is completed, and processsteps do not need to be added.
Owner:RUIAN VEHICLE FITTING FACTORY

LED chip with capacitive structure and preparation method thereof

The invention provides a light-emitting diode (LED) chip with a capacitance structure and a preparation method thereof. The LED chip comprises an N-type semiconductor layer, a multi-quantum well light-emitting layer, a P-type semiconductor layer, an N electrode and a P electrode, wherein the N electrode is electrically connected with the N-type semiconductor layer, the P electrode is electrically connected with the P-type semiconductor layer, the LED chip is electrically connected with the capacitance structure, the capacitance structure comprises a first conductive layer, a second conductive layer and a dielectric material layer, the first conductive layer and the second conductive layer are parallel to each other and are arranged at intervals, the dielectric material layer is arranged between the first conductive layer and the second conductive layer, the first conductive layer is electrically connected with the P electrode, the second conductive layer is electrically connected with the N electrode, and the first conductive layer and the second conductive layer in the capacitance structure and the P electrode and the N electrode of the LED chip are arranged in parallel. By additionally arranging the capacitance structure on the LED chip, the capacitance structure can play a protection role on the LED chip, ripple can be filtered, surge impact is prevented, and the reliability of the LED chip is improved.
Owner:FOCUS LIGHTINGS SCI & TECH

A Lateral Insulated Gate Bipolar Transistor with Low Turn-on Overshoot Current

ActiveCN110190120BNo drop in current capabilityCurrent capability does not affectThyristorEngineeringPolysilicon gate
A lateral insulated gate bipolar transistor with low turn-on overshoot current reduces the current peak value flowing through the device when the second gate pulse is turned on without reducing the current capability and withstand voltage capability. The semiconductor has: a buried oxygen on a P-type substrate, an N-type drift region on the buried oxygen, a P-type body region and an N-type buffer zone on it, and a P-type collector in the N-type buffer zone region, a field oxygen layer is provided above the N-type drift region, a P-type well region is provided in the P-type body region, a P-type emitter region and an emitter region are arranged in the P-type well region, and the inside of the above-mentioned 4 regions The boundary is synchronously invaginated to form a pinch-off region. The surface of the P-type body region is provided with a gate oxide layer, and the gate oxide layer is provided with a polysilicon gate electrode, and the polysilicon gate electrode is composed of the first gate electrode located above the surface of the P-type body region and the pinch-off region and the N-type drift region. Composed of the second grid electrode, the first grid electrode is connected to the first grid resistor, and the second grid electrode is connected to the second grid resistor.
Owner:SOUTHEAST UNIV
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