[0035] Example 1
[0036] Attached to the following Figures 2 to 8 The method for fabricating the semiconductor structure provided by the embodiment of the present invention will be described in detail.
[0037] First, perform step S10, please refer to figure 2 , a semiconductor substrate 101 is provided, and the semiconductor substrate has a plurality of trenches 103 . To simplify, figure 2 Only one groove is shown in .
[0038] The semiconductor substrate 101 may be monocrystalline silicon or polycrystalline silicon, or may be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like, or may be a composite structure such as silicon-on-insulator. Those skilled in the art can select the type of the semiconductor substrate 101 according to the semiconductor device formed on the semiconductor substrate 101, so the type of the semiconductor substrate 101 should not limit the protection scope of the present invention.
[0039] In a specific embodiment, the trench 103 is used as an isolation structure to provide isolation for the active regions on both sides of the trench 103, and a MOS transistor or a fin field effect can be formed on the active regions on both sides of the trench 103 transistors and other semiconductor devices.
[0040] The trench 103 may be formed in the semiconductor substrate 101 using an etching process (dry etching or wet etching process). When the trench 103 is formed by an etching process, a pad oxide layer 1021 and a pad nitride layer 1022 may be sequentially formed on the semiconductor substrate 101 as an etch stop layer 102 to protect the semiconductor substrate 101 , and then perform an etching process to form the trench 103 .
[0041] The trench 103 may have vertical sidewalls or non-vertical sidewalls. In the method for fabricating the semiconductor structure according to the embodiment of the present invention, the shape and size of the trench 103 are not particularly limited. The semiconductor structure formed by the method for fabricating the semiconductor structure provided in the embodiment of the present invention has a particularly significant improvement effect on void defects.
[0042] Next, perform step S12, please refer to image 3 and Figure 4 , a first silicon oxide layer 104 and a nitrogen-doped silicon oxide layer 105 are sequentially formed on the bottom and sidewalls of the trench 103 . The material of the first silicon oxide layer 104 may specifically be silicon dioxide, and the material of the nitrogen-doped silicon oxide layer 105 may specifically be SiO x N y.
[0043] The first silicon oxide layer 104 and the nitrogen-doped silicon oxide layer 105 may be formed in the same machine, and the machine at least includes a first process chamber and a second process chamber, wherein the first silicon oxide The layer 104 is formed in the first process chamber, for example, and the nitrogen-doped silicon oxide layer 105 is formed in the second process chamber, for example.
[0044] Specifically, the first silicon oxide layer 104 may be formed by an in-situ steam generation (In Situ Steam Generation, ISSG) process or a thermal chemical vapor deposition (TCVD, Thermal CVD) process. In this embodiment, the first silicon oxide layer 104 is grown by an in-situ steam generation process, and the thickness of the first silicon oxide layer 104 is 50 Å to 200 Å. The formed first silicon oxide layer 104 can repair the lattice defects of the substrate in the trench 103 and improve the surface pressure of the substrate in the trench 103, and can also protect the substrate surface in the trench 103. Prevent the subsequent filling process from damaging the substrate.
[0045] In the in-situ steam generation process, the temperature of the production process can be set according to actual needs, and preferably, the temperature of the production process is 800°C-1100°C.
[0046]In the in-situ steam generation process, the time of the production process can be set according to actual needs, and preferably, the time of the production process is 10s-50s.
[0047] In the in-situ steam generation process, the gas of the production process is N 2 O and H 2 , the gas flow can be set according to actual needs, preferably, the gas flow is 20slm-100slm and 0-1slm.
[0048] In the in-situ steam generation process, the gas pressure of the production process can be set according to actual needs, and preferably, the gas pressure is 10 torr to 50 torr.
[0049] The nitrogen-doped silicon oxide layer 105 can be formed by injecting nitrogen plasma into the first silicon oxide layer 104 by using a decoupled plasma nitridation (DPN, decoupled plasma nitridation). The DPN process uses RF (radio frequency) to generate nitrogen plasma with high density but a small electron temperature, and injects nitrogen plasma into the surface layer (for example, 1 Å -10 Å) of the first silicon oxide layer 104 , thereby The nitrogen-doped silicon oxide layer 105 is formed on the surface of the first silicon oxide layer 104 .
[0050] The power of the nitrogen plasma injected into the first silicon oxide layer 104 by the decoupling plasma nitridation process is 0W˜2kw. Of course, in other examples, the power can also be adjusted to other values according to actual needs. In the decoupling plasma nitridation process, the nitrogen doping concentration of the nitrogen-doped silicon oxide layer 105 can be set according to actual needs, and preferably, the doping concentration of the nitrogen-doped silicon oxide layer 105 is 1E 15 /cm 2 -7E 15 /cm 2.
[0051] After the nitrogen-doped silicon oxide layer 105 is formed, a plasma nitridation annealing process (PNA, plasmanitridation anneal) is performed, and the obtained semiconductor structure is placed in a nitrogen-oxygen mixed atmosphere for annealing. This process is mainly used to repair the lattice loss in the first silicon oxide layer 104 and adjust the distribution of the nitrogen plasma.
[0052] In the plasma nitridation annealing process, the temperature of the annealing treatment can be set according to actual needs, and preferably, the temperature of the annealing treatment is 800°C to 1100°C.
[0053] In the plasma nitridation annealing process, the time of the annealing treatment can be set according to actual needs, and preferably, the time of the annealing treatment is 50s˜200s.
[0054] In the plasma nitridation annealing process, the pressure of the process chamber for the annealing treatment can be set according to actual needs, and preferably, the pressure of the process chamber for the annealing treatment is 20torr-100torr.
[0055] In a specific embodiment, when the plasma nitridation annealing process is performed, the obtained semiconductor structure can be placed in a PNA process chamber first, and a nitrogen-oxygen mixed gas is introduced into the process chamber, and then the process is Heating is performed in the chamber, and when the temperature in the process chamber reaches the annealing temperature (eg, 800° C.-1100° C.), the temperature is kept for a certain period of time (eg, 50s-200s), so that the nitrogen plasma is heated in the first silicon oxide layer 104 Internal diffusion is performed to form the nitrogen-doped silicon oxide layer 105 , and the temperature is finally lowered to room temperature.
[0056] In a preferred solution, the formation of the first silicon oxide layer 104 , the formation of the nitrogen-doped silicon oxide layer 105 and the PNA process are all performed in different process chambers of the same machine, so as to avoid the semiconductor structure entering and leaving multiple machines. Introduce unnecessary pollution.
[0057] Next, the nitrogen-doped silicon oxide layer on the sidewall of the trench in this embodiment replaces the growth control layer on the sidewall of the trench in the prior art. In the prior art, the sidewall of the trench needs to use an ALD process to grow the control layer. In this embodiment, the steps of the control layer are reduced, and the physical thickness of the sidewall of the trench is not increased, the aspect ratio of the trench is not increased, and the difficulty of filling the trench is not increased.
[0058] Step S30 is executed, please refer to Figure 5 , etching and removing part of the nitrogen-doped silicon oxide layer 105 to expose the first silicon oxide layer 104 at the bottom of the trench 103 .
[0059] In this step, a dry etching process may be used to remove part of the nitrogen-doped silicon oxide layer 105. When the material of the nitrogen-doped silicon oxide layer 105 is selected to be silicon oxynitride, the main gas for etching may be CF 4 , can also include O 2 , CO, Ar, CHF 3 one or more of them.
[0060] Next, step S40 is executed. For details, please refer to Figure 6-8 , a high aspect ratio process (HARP, High Aspect Ratio Process) can be used to form the second silicon dioxide layer, the second silicon dioxide layer including the first part of the second silicon dioxide layer, the second part of the second silicon dioxide layer and the second silicon dioxide layer. A third portion of the silicon oxide layer is formed by a first high aspect ratio deposition process, a second high aspect ratio deposition process and a third high aspect ratio deposition process, the first high aspect ratio deposition process, the second high aspect ratio deposition process The gas flow rates used for the deposition process and the third high aspect ratio deposition process are different.
[0061] In specific implementation, a first high aspect ratio deposition process can be used to form the first portion 106 of the second silicon dioxide layer, and the first portion 106 of the second silicon dioxide layer covers the nitrogen doped on the sidewall of the trench 103 The surface of the hetero silicon oxide layer 105 and the exposed surface of the first silicon oxide layer 104 . The thickness of the first portion 106 of the second silicon dioxide layer is relatively thin, and the thickness of the first portion 106 of the second silicon dioxide layer in the trench 103 is, for example, 500Å-1000Å. In the first high aspect ratio deposition process, the process gas includes TEOS (ethyl orthosilicate) and O 3 , preferably, the TEOS flow is first passed into 500sccm-1500sccm, and then rises to 1000sccm-3000sccm, O 3 The flow rate is 10000sccm-30000sccm.
[0062] In a specific implementation, a second high aspect ratio deposition process may be used to form the second portion 107 of the second silicon dioxide layer, and the second portion 107 of the second silicon dioxide layer covers the first portion 106 of the second silicon dioxide layer. The thickness of the second part 107 of the second silicon dioxide layer in the trench 103 is 500Å-1500Å, and the trench 103 is filled up. Of course, in other embodiments, the second portion 107 of the second silicon dioxide layer may not fill the trench 103 . In the second high aspect ratio deposition process, the process gas includes TEOS and O3, preferably, the flow rate of TEOS is 1500sccm-3500sccm, O 3 The flow rate is 10000sccm-30000sccm.
[0063] In specific implementation, a third high aspect ratio deposition process may be used to form the third portion 108 of the second silicon dioxide layer, and the third portion 108 of the second silicon dioxide layer covers the second portion 107 of the second silicon dioxide layer . The thickness of the third portion 108 of the second silicon dioxide layer above the trench 103 is thicker than that of the first portion 106 of the second silicon dioxide layer and the second portion 107 of the second silicon dioxide layer, eg, 2000Å-5000Å. In the third high aspect ratio deposition process, the process gas includes TEOS, O 3 and O 2 , preferably, the TEOS flow is 4000sccm-7000sccm, O 3 The flow is 10000sccm-30000sccm, O 2 The flow is 10000sccm-20000sccm.
[0064] The process temperature in the first high aspect ratio deposition process, the second high aspect ratio deposition process and the third high aspect ratio deposition process can be set according to actual needs. Preferably, in this embodiment, the process temperature is 400℃-800℃.
[0065] The pressures of the above-mentioned processes in the first high aspect ratio deposition process, the second high aspect ratio deposition process and the third high aspect ratio deposition process can be set according to actual needs. Preferably, in this embodiment, the process pressure The pressure is 400torr-1000torr.
[0066] When the second silicon dioxide layer is formed, the growth rate of the second silicon dioxide layer on the surface of the first silicon oxide layer 104 is greater than that on the nitrogen-doped silicon oxide layer 105 , namely , the growth rate of the second silicon dioxide layer at the bottom of the trench 103 is greater than the growth rate of the second silicon dioxide layer on the sidewall of the trench 103 , therefore, the growth of the silicon oxide layer on the sidewall of the trench 103 can be avoided. Too fast will lead to the phenomenon of premature sealing, which can avoid void defects.
[0067] At the same time, since the formation of the first silicon oxide layer 104 and the nitrogen-doped silicon oxide layer 105 and the PNA process are all performed in different process chambers of the same machine, the semiconductor structure is prevented from entering and exiting multiple machines and causing pollution.
[0068] Using the decoupling plasma nitridation process to form the nitrogen-doped silicon oxide layer 105 does not increase the physical thickness of the sidewall of the trench 103, does not increase the aspect ratio of the trench 103, and does not increase the overall thickness of the trench 103. The difficulty of filling the trench 103 is described.
[0069] In this embodiment, when the nitrogen-doped silicon oxide layer 105 at the bottom of the trench 103 is removed by etching, the morphology of the top corner of the trench 103 will not be damaged, and the electrical performance of the device will not be affected.
