Memory structure and method of forming the same

Abstract

The present invention relates to a memory structure and a forming method thereof. The memory structure includes: a first base, including: a substrate layer and a storage layer, the substrate layer has a first surface and a second surface opposite to each other, and the storage layer is located on On the first surface of the substrate layer, the first substrate includes a pad area; a dielectric layer located on the second surface of the substrate layer; a solder pad located on the surface of the dielectric layer on the pad area; isolation The structure penetrates through the substrate layer, is located at the edge of the pad region, surrounds the substrate layer in the pad region, and is used to isolate the substrate layer in the pad region from the substrate layer around the isolation structure. In the memory structure of the present invention, the parasitic capacitance between the pad and the substrate layer is reduced, which is beneficial to improving memory performance.

Description

technical field [0001] The invention relates to the field of semiconductor technology, in particular to a memory structure and a forming method thereof. Background technique [0002] In recent years, the development of flash memory (Flash Memory) is particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. Has been widely used. In order to further increase the bit density (Bit Density) of the flash memory while reducing the bit cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been developed rapidly. [0003] The 3D NAND flash memory structure includes a storage array structure and a CMOS circuit structure above the storage array structure. The storage array structure and the CMOS circuit structure are usually formed on two different wafers, and then bonded to The CMOS circuit wafer is bo...

AI Technical Summary

Problems solved by technology

However, due to the need to open the insulating layer and the wafer to form through-wafer vias at the same time for circuit connection, the increase in the thickness of the insulating layer will lead to an increase in the aspect ratio of the through-wafer vias, and it is also necessary to strictly control the feature size and shape of the through-wafer vias. In appearance, the deviation of the process may lead to circuit breakage or leakage, which greatly increases the difficulty of the process, requires more advanced semiconductor processing machines, and increases the cost of the process.

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