Semiconductor device with raised doped crystal structure

Abstract

Semiconductor devices including raised or raised crystalline structures extending from device layers are described. In an embodiment, a III-N transistor includes raised crystalline n+ doped source / drain structures on either side of the gate stack. In an embodiment, an amorphous material is used to confine the growth of polycrystalline source / drain material, allowing high-quality source / drain doped crystals to grow from the undamaged region and expand laterally to form the two Low-resistance junction of 2-degree electron gas (2DEG). In some embodiments, regions of damaged GaN that could cause competing polycrystalline polygrowth are covered with amorphous material prior to initiation of raised source / logic growth.

Description

technical field [0001] The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor devices having raised doped crystal structures. Background technique [0002] Demand for integrated circuits (ICs) in portable electronic applications has motivated higher levels of semiconductor device integration. Many advanced semiconductor devices under development affect non-silicon semiconductor materials, including compound semiconductor materials (eg, GaAs, InP, InGaAs, InAs, and III-N materials). III-N materials, as well as other materials with wurtzite crystallinity such as but not limited to AgI, ZnO, CdS, CdSe, α-SiC, and BN, have shown promise for high voltage and high frequency applications such as power management ICs and RF specific future for power amplifiers). III-N heteroepitaxial (heterostructure) field-effect transistors (HFETs) such as high electron mobility transistors (HEMTs) and metal-oxide semiconductor (MOS) HEMTs) empl...

AI Technical Summary

Problems solved by technology

[0003] For many non-silicon device materials, it can be challenging to provide doped semiconductor materials suitable for making good ohmic contacts

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