Field effect transistor isolating structure and manufacturing method thereof

Abstract

The invention provides a field effect transistor isolating structure and a manufacturing method thereof. The field effect transistor isolating structure comprises a semiconductor substrate, a dielectric layer, a metal layer, an insulating layer, a contact window and a contact electrode. The semiconductor substrate has a field effect transistor area and an annular groove which surrounds the field effect transistor area. The dielectric layer is formed at the side wall and the bottom of the annular groove. The metal layer is filled in the annular groove. The upper-layer part of the metal layer iseliminated, thereby forming the annular groove. The insulating layer is filled in the annular groove for burying the metal layer. The contact window exposes the metal layer in the annular groove. Thecontact electrode is filled in the contact window and contacts with the metal layer. According to the isolating structure and the manufacturing method thereof, the novel isolating structure is utilized; electric leakage between the field effect transistors can be prevented without traditional shallow-groove isolating structures, and furthermore electric leakage prevention performance can be effectively improved. Compared with the traditional shallow-groove isolating structure, the field effect transistor isolating structure have advantages of greatly reducing area and effectively improving integration density of the field effect transistor.

Description

technical field [0001] The invention belongs to the field of semiconductor design and manufacture, in particular to an isolation structure of a field effect transistor and a manufacturing method thereof. Background technique [0002] Currently, semiconductor integrated circuits generally include active regions and isolation regions between the active regions, which are formed before the active devices are fabricated. As the semiconductor technology enters the deep sub-micron era, the isolation layer of the active region of the semiconductor device is mostly manufactured by the shallow trench isolation process (Shallow Trench Isolation, STI). [0003] The process steps of manufacturing a shallow trench isolation structure (STI) in the prior art generally include: [0004] 1) sequentially forming a hard mask and a photoresist on the semiconductor substrate; [0005] 2) Transfer the mask pattern to the hard mask pattern by etching with a high selectivity ratio, and then trans...

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Problems solved by technology

[0011] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide an isolation structure of a field-effect transistor and a manufacturing method thereof, which are used to solve the complicated manufacturing process of the shallow trench isolation structure (STI) adopted in the prior art, Poor anti-leakage performance and excessive occupied area

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