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Semiconductor base, semiconductor device, method for manufacturing semiconductor base, and method for manufacturing semiconductor device

A manufacturing method and semiconductor technology, which are applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., to achieve the effect of high pit suppression effect

Active Publication Date: 2018-06-08
SANKEN ELECTRIC CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] On the other hand, it is known that doping iron into the buffer layer will increase the vertical withstand voltage

Method used

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  • Semiconductor base, semiconductor device, method for manufacturing semiconductor base, and method for manufacturing semiconductor device
  • Semiconductor base, semiconductor device, method for manufacturing semiconductor base, and method for manufacturing semiconductor device
  • Semiconductor base, semiconductor device, method for manufacturing semiconductor base, and method for manufacturing semiconductor device

Examples

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Effect test

Embodiment 1

[0093] made as figure 1 Shown semiconductor substrate 10, described semiconductor substrate 10 is provided with buffer layer, and described buffer layer has Image 6 (b) Iron concentration distribution and boron concentration distribution shown. That is, in Example 1, a buffer layer is provided on the substrate 12 made of silicon. The buffer layer is composed of an initial layer made of AlN and a laminate in which GaN layers and AlN layers are alternately laminated. In the buffer layer of Embodiment 1, there is a reduced region and an increased region on the substrate 12, and the reduced region is that the boron concentration changes from the substrate 12 side to the channel layer 26 side by 3×10 19 atoms / cm 3 In a gradually decreasing area, the increasing area is arranged on the decreasing area and the iron concentration is increased from the substrate 12 side to the channel layer 26 side to 5×10 19 atoms / cm 3 In the increased area, after the boron concentration is suffic...

Embodiment 2

[0099] made as figure 1 Shown semiconductor substrate 10, described semiconductor substrate 10 is provided with buffer layer, and described buffer layer has Image 6 (c) The iron concentration distribution and the boron concentration distribution represented. That is, in Example 2, a buffer layer is provided on the substrate 12 made of silicon, and the buffer layer is composed of an initial layer made of AlN and a laminate in which GaN layers and AlN layers are alternately laminated. In the buffer layer of Example 2, there are reduced regions and increased regions on the substrate 12, and the reduced region is that the boron concentration changes from the substrate 12 side to the channel layer 26 side by 3×10 19 atoms / cm 3 In the gradually decreasing area, the increasing area is arranged on the channel layer 26 side from the position where the boron concentration starts to decrease and the iron concentration increases from the substrate 12 side to the channel layer 26 side t...

Embodiment 3

[0105] made as figure 1 Shown semiconductor substrate 10, described semiconductor substrate 10 is provided with buffer layer, and described buffer layer has Image 6 (f) Iron concentration distribution and boron concentration distribution shown. That is, in Example 3, a buffer layer is provided on the substrate 12 made of silicon, and the buffer layer is composed of an initial layer made of AlN and a laminate in which GaN layers and AlN layers are alternately laminated. In the buffer layer of Example 3, there are reduced regions and increased regions on the substrate 12, and the reduced region is that the boron concentration changes from the substrate 12 side to the channel layer 26 side by 3×10 19 atoms / cm 3 In the gradually decreasing area, the increasing area is arranged on the channel layer 26 side from the position where the boron concentration starts to decrease and the iron concentration increases from the substrate 12 side to the channel layer 26 side to 5×10 19 ato...

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Abstract

The present invention is a semiconductor base characterized in being provided with: a substrate; a buffer layer comprising a nitride semiconductor, the buffer layer being provided on the substrate; and a channel layer comprising a nitride semiconductor, the channel layer being provided on the buffer layer; the buffer layer including a first region provided on the substrate side so that the concentration of boron is higher than the concentration of an acceptor element, and a second region provided on the first region so that the concentration of boron is lower than the first region and the concentration of the acceptor element is higher than the first region. Consequently, the semiconductor base is provided so that a high pit suppressing effect can be obtained while maintaining high longitudinal pressure resistance.

Description

technical field [0001] The present invention relates to a semiconductor substrate, a semiconductor device, a method for manufacturing the semiconductor substrate, and a method for manufacturing the semiconductor device. Background technique [0002] The nitride semiconductor layer is generally formed on an inexpensive silicon substrate or a sapphire substrate. However, the lattice constants of these substrates are largely different from those of the nitride semiconductor layer, and also have different thermal expansion coefficients. Therefore, large strain energy occurs in the nitride semiconductor layer formed on the substrate by epitaxial growth. As a result, cracks are likely to occur in the nitride semiconductor layer and the crystal quality is lowered. [0003] Conventionally, in order to solve the above-mentioned problems, a buffer layer formed by laminating nitride semiconductor layers having different compositions has been arranged between a substrate and a functio...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/338H01L21/205H01L21/336H01L29/778H01L29/78H01L29/812
CPCH01L29/66462H01L29/7786H01L29/2003H01L29/36H01L21/02263H01L21/02329H01L21/0254H01L21/28H01L21/324H01L2924/10323H01L29/66431H01L29/7787
Inventor 鹿内洋志佐藤宪篠宫胜土屋庆太郎萩本和德
Owner SANKEN ELECTRIC CO LTD
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