Silicon-on-insulator flat panel display driver chip and preparation method thereof

Abstract

Display driver chip composed of high-voltage P-type lateral metallic oxide transistors, high-voltage N-type lateral metallic oxide transistors, high-pressure diodes and low-voltage devices, among the high-voltage devices and between the high-voltage and low-voltage devices are separated by double-groove filled with silicon dioxide that extending from a buried oxide layer through a N-type epitaxial layer to a field oxide layer on device surface, partial N-type or P-type heavily dosed buried layer are disposed above the buried oxide layer that positioning under the N-type lateral metallic oxide transistors and the high-pressure diodes. The prepartion method is: preparing a buried oxide layer on a P-type substrate, preparing partial N-type or P-type heavily dosed buried layer above the buried oxide layer, depositing a N-type epitaxial layer, preparing high-voltage P-wells for high-voltage N-type lateral metallic oxide transistors and high-pressure diodes, preparing P-type drift region for high-voltage N-type lateral metallic oxide transistors, then preparing buffer layer of high-voltage tubes, lower-voltage wells of lower-voltage devices, contact holes of source drain region, evaporating aluminum, carving aluminum reversely and forming electrodes and metallic field panel, passivation.

Description

technical field [0001] The invention relates to a display driver chip and a preparation method thereof, and is especially suitable for a row address driver chip and a column address driver chip for a plasma display (PDP). Background technique [0002] The plasma display driver chip is mainly composed of a low-voltage complementary lateral metal-oxide-semiconductor logic circuit controlling a high-voltage device output circuit. Although the size of the display screen is increasing, the chip that actually controls the display is developing towards a highly integrated, smaller size, higher frequency, lower power consumption, better performance, and lower cost. Since the low-voltage complementary lateral metal-oxide-semiconductor technology is basically mature and the power consumption is very low, the improvement of the overall performance of the driver chip is mainly focused on the design and process of the power device in addition to the improvement of the circuit level. At ...

AI Technical Summary

Problems solved by technology

However, in the traditional bulk silicon or buried layer process, in order to achieve a high voltage of more than 100V, the thickness of the external lamination layer is relatively high. At the same time, the substrate leakage current will increase the power consumption of the device due to the connection between the substrate and the device, and will affect the device. reliability, which in turn affects the performance and reliability of the entire chip; and the traditional high-voltage device isolation methods are mainly single-slot filled silicon dioxide and polysilicon isolation, deep junction isolation and pn junction self-isolation, these isolation methods take up a lot The proportion of the chip area, especially the pn junction isolation method, the area of ​​the chip used for isolation is more than 20%.

Images