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Comparator and successive approximation analog-to-digital converter

A comparator and inverter technology, applied in the direction of analog/digital conversion, code conversion, instruments, etc., can solve the problem of low speed of the comparator, and achieve the effect of increasing the speed and reducing the number of

Active Publication Date: 2018-07-10
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Description
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Problems solved by technology

[0004] However, the above comparator suffers from slow speed

Method used

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Embodiment Construction

[0023] The asynchronous successive approximation analog-to-digital converter (Successive Approximation Register Analog-to-Digital Converter, SAR DC) is a research hotspot in recent years. Compared with the traditional pipelined ADC, the asynchronous SAR ADC has the advantages of low power consumption and low cost , These advantages enable asynchronous SAR ADC to obtain a wide range of applications, such as portable battery-powered instruments, pen input quantizers, industrial control and data signal collectors, etc.

[0024] However, the asynchronous SAR ADC also has the problem of low maximum operating speed, and the reason for the low maximum operating speed of the SAR ADC is its internal comparator.

[0025] Currently, a typical comparator structure is as figure 1As shown, the comparator includes: a first pre-op-amp unit 11 suitable for sequentially amplifying the signal to be compared at various stages, including an op-amp subunit 121 and an op-amp subunit 121 symmetricall...

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Abstract

The invention provides a comparator and a successive approximation analog-to-digital converter. The comparator comprises a front operational amplifier circuit and a latch circuit which are connected in turn. The front operational amplifier circuit comprises first, second and third front operational amplifier units which are connected in turn and suitable for amplifying signals to be compared. Thethird front operational amplifier unit comprises first and second PMOS transistors. The latch circuit comprises a first CMOS phase inverter and a second CMOS phase inverter and is provided with a bistable structure formed by end-to-end connection of the inverters and is suitable for comparing the signals and outputting the corresponding digital signals according to the comparison result. The gateelectrodes of the first and second PMOS transistors are coupled with the output end of the second front operational amplifier unit. The gate electrode of the first NMOS transistor and the gate electrode of the second NMOS transistor are coupled with the output end of the second front operational amplifier unit and the input end of the third front operational amplifier unit. With application of thescheme, the speed of the comparator can be enhanced.

Description

technical field [0001] The invention relates to the technical field of integrated circuit devices, in particular to a comparator and a successive approximation analog-to-digital converter. Background technique [0002] Analog-to-Digital Converter (ADC) is the core module of today's applied electronic equipment and communication equipment. Due to the demand for portable electronic communication equipment in the electronic market in recent years, ADCs with low power consumption and high precision have become ADCs. Major trends in technology. As one of the main modules of the ADC structure, the comparator, especially the comparator with high speed and low power consumption, also plays an important role in the application market. [0003] Currently, a typical comparator structure is as figure 1 As shown, the comparator includes: a first pre-op amp unit 11, a second pre-op amp unit 12, and a third pre-op amp unit 13, which are suitable for sequentially amplifying the signals to...

Claims

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Application Information

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IPC IPC(8): H03K5/24H03M1/46
CPCH03K5/2481H03M1/462
Inventor 荀本鹏刘飞徐丽唐华杨海峰
Owner SEMICON MFG INT (SHANGHAI) CORP
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