Phase-locked loop starting circuit

Abstract

The invention provides a phase-locked loop starting circuit. The phase-locked loop starting circuit comprises a NOR gate, a first NAND gate, a second NAND gate, a self-adding counter, a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a fifth phase inverter, a transmission gate, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. According to the invention, a phase-locked loop is capable of presetting important internal nodes to bespecific level in controllable time, and therefore PLL starting and locking time is shortened, and the starting sequence of the whole loop can be controlled, and no change is caused by technology, voltage, and temperature.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a phase-locked loop starting circuit. Background technique [0002] With the rapid development of integrated circuit design and CMOS technology, integrated circuits have entered a system-on-chip (System on Chip, SoC) design stage. With the continuous improvement of electronic system complexity, integration and chip operating frequency, the requirements for the distribution quality and stability of on-chip clocks are also getting higher and higher. Phase-locked loop (Phase Locked Loop, PLL), as the clock source of the system on chip, is an important functional module in modern integrated circuit design, and is widely used in various SoC chips. [0003] The phase-locked loop is a negative feedback system that compares the output phase with the input phase, and uses an externally input reference signal to control the frequency and phase of the internal oscillation signal of...

AI Technical Summary

Problems solved by technology

The traditional phase-locked loop start-up circuit compares two analog voltages VREF1 and VREF2 with a comparator, and the generated signal is used as the enable signal of the entire loop. Due to the offset voltage (offset) of the comparator and the pull-down time of VCTRL will be affected by the process , voltage, and temperature, so the comparison result is not accurate, and the time for the comparator to flip is not fixed, which may cause abnormal startup status of the phase-locked loop

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