14T radiation-resistant static storage cell

Abstract

The invention discloses a 14T radiation-resistant static storage cell, which is capable of improving SEU (Single Event Upset) resistance, improving the speed of the 14T radiation-resistant static storage cell to a large extent under the situation that smaller cell area is sacrificed and reducing power consumption. During a reading-writing stage, a WL signal is in high level. When a circuit is in awriting stage, if BL is in high level and BLB is in low level, '1' can be written in a storage node Q through differential input transistors N4 and N5; if the BL is in low level and the BLB is in high level, '0' can be written in the storage node Q through the differential input transistors N4 and N5. When the circuit is in a reading stage, if the BL and the BLB are both in high level and data stored in the cell unit is '1' voltage can be discharged to the ground through transistors N4 and N0 by the BLB, voltage difference can be generated by a bit line, and then the data can be read out through a sensitive amplifier; if the data stored in the cell circuit is '0', the current can be discharged to the ground through transistors N5 and N1 by the BL, the voltage difference can be generated by the bit line, and then the data can be read out through the sensitive amplifier.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a unit circuit structure capable of increasing the writing speed of a storage unit, reducing unit power consumption and improving the ability of the unit to resist Single Event Upset (abbreviated as SEU). It is a 14T Radiation-resistant static storage unit. Background technique [0002] With the reduction of feature size and power supply voltage, the circuit is more and more sensitive to radiation, and the single event effect (Single Event Effect, abbreviated as SEE) becomes an inevitable problem, which makes the development of SEE radiation resistance hardening technology in combinational circuits very urgent. . SEU is a form of SEE, which is a soft error and non-destructive. When heavy ion particles are incident on the semiconductor material, the excess charges will be ionized, and these excess charges will be collected by the electrodes of the device, resulting in er...

AI Technical Summary

Problems solved by technology

Compared with the traditional six-tube unit and Dual Interlocked Storage Cell (DICE) structure, it has better anti-SEU ability, but the unit has poor write margin and consumes a lot of power

[0004] 2) if figure 2 and image 3 The two NovelSort Error Hardened 10T SRAM Cells circuits proposed by In-Seok Jung and Yong-Bin Kim in 2012 are hardened NMOS stacked 10T SRAM cell (NS10T) and hardened PMOS stacked 10T SRAM cell (PS10T). structure, in which the NS10T circuit can only restore the flip from 0 to 1, and the PS10T can only restore the flip from 1 to 0, and both circuits can solve the problem of multi-node disturbance caused by charge sharing, but the two circuits Slow write speed and high power consumption

But this circuit has slow write speed and poor read ability

[0006] 4) if Figure 5 Shown is a Highly ReliableMemory Cell (RHD12T) circuit proposed by Chunhua Qi and Liyi Xiao in 2016. This circuit greatly enhances the anti-SEU ability of the circuit by using source isolation technology. It can not only improve the anti-SEU ability of a single node but also It can improve the ability to resist multi-node flipping, but the writing speed of this circuit is slow and the power consumption is large

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