Design Method of Heterogeneous Reconfigurable Graph Computing Accelerator System Based on FPGA

A design method and accelerator technology, applied in computer-aided design, CAD circuit design, calculation, etc., can solve the problems of inefficient software level, low effective calculation rate, and low off-chip bandwidth utilization, and achieve low power consumption and acceleration Effect of Graph Algorithms

Active Publication Date: 2020-12-04
UNIV OF SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the design and implementation of graph computing systems at the software level, there are often some inefficient and unavoidable problems at the software level, such as low utilization of off-chip bandwidth and low effective computing rate.

Method used

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  • Design Method of Heterogeneous Reconfigurable Graph Computing Accelerator System Based on FPGA
  • Design Method of Heterogeneous Reconfigurable Graph Computing Accelerator System Based on FPGA
  • Design Method of Heterogeneous Reconfigurable Graph Computing Accelerator System Based on FPGA

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Embodiment

[0055] FPGA in the embodiment of the present invention refers to Field Programmable Gate Arrays (Field Programmable GateArrays), and the system designed in the present invention is a heterogeneous system based on PC-FPGA, wherein, the data path between PC and FPGA can adopt PCI-E bus protocol. The data path inside the FPGA on-chip accelerator is illustrated by using the AXI bus protocol as an example to illustrate the data path in the drawings of the embodiments of the present invention, but the present invention is not limited thereto.

[0056] figure 1 It is a flowchart of an FPGA-based graph computing accelerator design method 100 according to an embodiment of the present invention. The method 100 includes:

[0057] S110, load the driver program required by the hardware device module, select a suitable computing engine according to the graph data to be processed, if the third type of computing engine is selected, preprocess the graph data, and transmit the preprocessed gr...

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Abstract

The invention discloses a design method of an FPGA-based heterogeneous reconfigurable graph computing accelerator system. The entire accelerator system includes two heterogeneous modules, PC and FPGA. Open the PCIe DMA and other devices; select the graph computing accelerator engine according to the number of vertices and edges of the graph data to be processed; preprocess the graph data after selecting the accelerator engine; pass the preprocessed graph data through PCIe DMA transfers to the onboard DDR of the FPGA development board; the startup accelerator starts to read the graph data from the address specified by the onboard DDR; the controller distributes the graph data to different processing units for processing and calculation; after each processing unit is calculated and processed After the data is collected, the result is sent to the calculation result collection module; the collection module writes the result back to the onboard DDR, and after the entire graph data is processed, the PC reads the result from the onboard DDR. The invention has the characteristics of high performance, high energy efficiency, low power consumption and the like.

Description

technical field [0001] The invention relates to the field of computer hardware acceleration, in particular to an FPGA-based graph computing accelerator system design method. Background technique [0002] In the real world, a graph can be used to represent the relationship between different entities. It is an abstraction of the relationship model between entities. A lot of information can be stored in the graph structure, so it has a wide range of applications in practice, such as: social network Analysis, web page map search, product recommendation system establishment, traffic network analysis, and biomedical information analysis, etc. In today's era of big data, the scale of graphs is becoming larger and larger. For example, the number of Facebook users reached 2.2 billion in July 2014, and the number of relationships between users reached hundreds or even hundreds of billions. If the relationship between these users Stored in the form of graph edges, the storage capacity...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/34G06F117/08
CPCG06F30/331G06F2117/08
Inventor 周学海李曦王超陈香兰
Owner UNIV OF SCI & TECH OF CHINA
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